diff options
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SOPInstructions.td | 12 | ||||
| -rw-r--r-- | llvm/test/MC/AMDGPU/data.s | 22 | ||||
| -rw-r--r-- | llvm/test/MC/AMDGPU/sopk.s | 12 | ||||
| -rw-r--r-- | llvm/test/MC/Disassembler/AMDGPU/sopk_gfx9.txt | 9 |
4 files changed, 44 insertions, 11 deletions
diff --git a/llvm/lib/Target/AMDGPU/SOPInstructions.td b/llvm/lib/Target/AMDGPU/SOPInstructions.td index 3b5c3d0d552..aa334a3a885 100644 --- a/llvm/lib/Target/AMDGPU/SOPInstructions.td +++ b/llvm/lib/Target/AMDGPU/SOPInstructions.td @@ -672,6 +672,16 @@ def S_SETREG_IMM32_B32 : SOPK_Pseudo < } // End hasSideEffects = 1 +let SubtargetPredicate = isGFX9 in { + def S_CALL_B64 : SOPK_Pseudo< + "s_call_b64", + (outs SReg_64:$sdst), + (ins s16imm:$simm16), + "$sdst, $simm16"> { + let isCall = 1; + } +} + //===----------------------------------------------------------------------===// // SOPC Instructions //===----------------------------------------------------------------------===// @@ -1333,6 +1343,8 @@ def S_SETREG_B32_vi : SOPK_Real_vi <0x12, S_SETREG_B32>; def S_SETREG_IMM32_B32_vi : SOPK_Real64<0x14, S_SETREG_IMM32_B32>, Select_vi<S_SETREG_IMM32_B32.Mnemonic>; +def S_CALL_B64_vi : SOPK_Real_vi <0x15, S_CALL_B64>; + //===----------------------------------------------------------------------===// // SOP1 - GFX9. //===----------------------------------------------------------------------===// diff --git a/llvm/test/MC/AMDGPU/data.s b/llvm/test/MC/AMDGPU/data.s index c967534b2e5..2800b672483 100644 --- a/llvm/test/MC/AMDGPU/data.s +++ b/llvm/test/MC/AMDGPU/data.s @@ -4,13 +4,13 @@ .text v_mov_b32 v7, s24 - v_mov_b32 v8, s25 - .long 0xabadc0de - s_nop 0 - s_endpgm - .long 0xbadc0de1, 0xbadc0de2, 0xbadc0de3, 0xbadc0de4 - .byte 0x0a, 0x0b - .byte 0x0c + v_mov_b32 v8, s25 + .long 0xabadc0de + s_nop 0 + s_endpgm + .long 0xabadc0d1, 0xabadc0d2, 0xabadc0d3, 0xabadc0d4 + .byte 0x0a, 0x0b + .byte 0x0c // CHECK: .text // CHECK: v_mov_b32 @@ -18,10 +18,10 @@ // CHECK: .long 0xabadc0de // CHECK_SAME: : ABADC0DE // CHECK: s_endpgm -// CHECK: .long 0xbadc0de1 -// CHECK: .long 0xbadc0de2 -// CHECK: .long 0xbadc0de3 -// CHECK: .long 0xbadc0de4 +// CHECK: .long 0xabadc0d1 +// CHECK: .long 0xabadc0d2 +// CHECK: .long 0xabadc0d3 +// CHECK: .long 0xabadc0d4 // CHECK: .byte 0x0a, 0x0b, 0x0c // CHECK-SAME: : 0A 0B 0C // CHECK-NOT: .long diff --git a/llvm/test/MC/AMDGPU/sopk.s b/llvm/test/MC/AMDGPU/sopk.s index 35e6c579563..522239e8d75 100644 --- a/llvm/test/MC/AMDGPU/sopk.s +++ b/llvm/test/MC/AMDGPU/sopk.s @@ -175,3 +175,15 @@ s_setreg_imm32_b32 hwreg(HW_REG_GPR_ALLOC, 1, 31), 0xff s_endpgm_ordered_ps_done // GFX9: s_endpgm_ordered_ps_done ; encoding: [0x00,0x00,0x9e,0xbf] // NOSICIVI: error: instruction not supported on this GPU + +s_call_b64 s[12:13], 12609 +// GFX9: s_call_b64 s[12:13], 0x3141 ; encoding: [0x41,0x31,0x8c,0xba] +// NOSICIVI: error: instruction not supported on this GPU + +s_call_b64 s[100:101], 12609 +// GFX9: s_call_b64 s[100:101], 0x3141 ; encoding: [0x41,0x31,0xe4,0xba] +// NOSICIVI: error: instruction not supported on this GPU + +s_call_b64 s[10:11], 49617 +// GFX9: s_call_b64 s[10:11], 0xc1d1 ; encoding: [0xd1,0xc1,0x8a,0xba] +// NOSICIVI: error: instruction not supported on this GPU diff --git a/llvm/test/MC/Disassembler/AMDGPU/sopk_gfx9.txt b/llvm/test/MC/Disassembler/AMDGPU/sopk_gfx9.txt index 1e7d8901b8b..7d8159f9eff 100644 --- a/llvm/test/MC/Disassembler/AMDGPU/sopk_gfx9.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/sopk_gfx9.txt @@ -2,3 +2,12 @@ # GFX9: s_endpgm_ordered_ps_done ; encoding: [0x00,0x00,0x9e,0xbf] 0x00,0x00,0x9e,0xbf + +# GFX9: s_call_b64 s[10:11], 0x3141 ; encoding: [0x41,0x31,0x8a,0xba] +0x41,0x31,0x8a,0xba + +# GFX9: s_call_b64 s[100:101], 0x3141 ; encoding: [0x41,0x31,0xe4,0xba] +0x41,0x31,0xe4,0xba + +# GFX9: s_call_b64 s[10:11], 0xc1d1 ; encoding: [0xd1,0xc1,0x8a,0xba] +0xd1,0xc1,0x8a,0xba |
