diff options
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 12 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AArch64/aarch64-vuzp.ll | 17 |
2 files changed, 24 insertions, 5 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index 407c81d14a2..3170fdcab63 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -6777,11 +6777,17 @@ SDValue AArch64TargetLowering::LowerBUILD_VECTOR(SDValue Op, const SDNode *N = V.getNode(); if (!isa<ConstantSDNode>(N->getOperand(1))) break; + SDValue N0 = N->getOperand(0); // All elements are extracted from the same vector. - if (!Vector) - Vector = N->getOperand(0).getNode(); - else if (Vector != N->getOperand(0).getNode()) { + if (!Vector) { + Vector = N0.getNode(); + // Check that the type of EXTRACT_VECTOR_ELT matches the type of + // BUILD_VECTOR. + if (VT.getVectorElementType() != + N0.getValueType().getVectorElementType()) + break; + } else if (Vector != N0.getNode()) { Odd = false; Even = false; break; diff --git a/llvm/test/CodeGen/AArch64/aarch64-vuzp.ll b/llvm/test/CodeGen/AArch64/aarch64-vuzp.ll index 51866fa1702..40e6a2d7938 100644 --- a/llvm/test/CodeGen/AArch64/aarch64-vuzp.ll +++ b/llvm/test/CodeGen/AArch64/aarch64-vuzp.ll @@ -1,4 +1,6 @@ -; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s +; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s + +declare <16 x i8> @llvm.aarch64.neon.tbl1.v16i8(<16 x i8>, <16 x i8>) ; CHECK-LABEL: fun1: ; CHECK: uzp1 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b @@ -48,4 +50,15 @@ entry: ret i32 undef } -declare <16 x i8> @llvm.aarch64.neon.tbl1.v16i8(<16 x i8>, <16 x i8>) +; CHECK-LABEL: pr36582: +; Check that this does not ICE. +define void @pr36582(i8* %p1, i32* %p2) { +entry: + %x = bitcast i8* %p1 to <8 x i8>* + %wide.vec = load <8 x i8>, <8 x i8>* %x, align 1 + %strided.vec = shufflevector <8 x i8> %wide.vec, <8 x i8> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6> + %y = zext <4 x i8> %strided.vec to <4 x i32> + %z = bitcast i32* %p2 to <4 x i32>* + store <4 x i32> %y, <4 x i32>* %z, align 4 + ret void +} |
