diff options
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp | 19 | ||||
| -rw-r--r-- | llvm/test/MC/Disassembler/ARM/arm-tests.txt | 3 |
2 files changed, 13 insertions, 9 deletions
diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp index 7900f9960ad..d4cd0879129 100644 --- a/llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp +++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp @@ -532,17 +532,18 @@ static bool BadRegsMulFrm(unsigned Opcode, uint32_t insn) { switch (Opcode) { default: // Did we miss an opcode? - assert(0 && "Unexpected opcode!"); + DEBUG(errs() << "BadRegsMulFrm: unexpected opcode!"); return false; case ARM::MLA: case ARM::MLS: case ARM::SMLABB: case ARM::SMLABT: case ARM::SMLATB: case ARM::SMLATT: case ARM::SMLAWB: case ARM::SMLAWT: - case ARM::SMMLA: case ARM::SMMLS: case ARM::USADA8: + case ARM::SMMLA: case ARM::SMMLAR: case ARM::SMMLS: case ARM::SMMLSR: + case ARM::USADA8: if (R19_16 == 15 || R15_12 == 15 || R11_8 == 15 || R3_0 == 15) return true; return false; - case ARM::MUL: case ARM::SMMUL: case ARM::SMULBB: case ARM::SMULBT: - case ARM::SMULTB: case ARM::SMULTT: case ARM::SMULWB: case ARM::SMULWT: - case ARM::SMUAD: case ARM::SMUADX: + case ARM::MUL: case ARM::SMMUL: case ARM::SMMULR: + case ARM::SMULBB: case ARM::SMULBT: case ARM::SMULTB: case ARM::SMULTT: + case ARM::SMULWB: case ARM::SMULWT: case ARM::SMUAD: case ARM::SMUADX: // A8.6.167 SMLAD & A8.6.172 SMLSD case ARM::SMLAD: case ARM::SMLADX: case ARM::SMLSD: case ARM::SMLSDX: case ARM::USAD8: @@ -562,14 +563,14 @@ static bool BadRegsMulFrm(unsigned Opcode, uint32_t insn) { } // Multiply Instructions. -// MLA, MLS, SMLABB, SMLABT, SMLATB, SMLATT, SMLAWB, SMLAWT, SMMLA, SMMLS, -// SMLAD, SMLADX, SMLSD, SMLSDX, USADA8 (for convenience): +// MLA, MLS, SMLABB, SMLABT, SMLATB, SMLATT, SMLAWB, SMLAWT, SMMLA, SMMLAR, +// SMMLS, SMMLAR, SMLAD, SMLADX, SMLSD, SMLSDX, and USADA8 (for convenience): // Rd{19-16} Rn{3-0} Rm{11-8} Ra{15-12} // But note that register checking for {SMLAD, SMLADX, SMLSD, SMLSDX} is // only for {d, n, m}. // -// MUL, SMMUL, SMULBB, SMULBT, SMULTB, SMULTT, SMULWB, SMULWT, SMUAD, SMUADX, -// USAD8 (for convenience): +// MUL, SMMUL, SMMULR, SMULBB, SMULBT, SMULTB, SMULTT, SMULWB, SMULWT, SMUAD, +// SMUADX, and USAD8 (for convenience): // Rd{19-16} Rn{3-0} Rm{11-8} // // SMLAL, SMULL, UMAAL, UMLAL, UMULL, SMLALBB, SMLALBT, SMLALTB, SMLALTT, diff --git a/llvm/test/MC/Disassembler/ARM/arm-tests.txt b/llvm/test/MC/Disassembler/ARM/arm-tests.txt index e5a3a768597..ee0ced146a1 100644 --- a/llvm/test/MC/Disassembler/ARM/arm-tests.txt +++ b/llvm/test/MC/Disassembler/ARM/arm-tests.txt @@ -278,3 +278,6 @@ # CHECK: uqsax r5, r6, r7 0x57 0x5f 0x66 0xe6 + +# CHECK: smmlareq r0, r0, r0, r0 +0x30 0x00 0x50 0x07 |
