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-rw-r--r--llvm/lib/Target/Hexagon/BitTracker.cpp4
-rw-r--r--llvm/lib/Target/Hexagon/BitTracker.h9
-rw-r--r--llvm/lib/Target/Hexagon/HexagonBitTracker.cpp29
-rw-r--r--llvm/lib/Target/Hexagon/HexagonCommonGEP.cpp35
4 files changed, 27 insertions, 50 deletions
diff --git a/llvm/lib/Target/Hexagon/BitTracker.cpp b/llvm/lib/Target/Hexagon/BitTracker.cpp
index cb7e633fb82..111d3b4d01f 100644
--- a/llvm/lib/Target/Hexagon/BitTracker.cpp
+++ b/llvm/lib/Target/Hexagon/BitTracker.cpp
@@ -868,7 +868,7 @@ void BT::visitNonBranch(const MachineInstr *MI) {
continue;
bool Changed = false;
- if (!Eval || !ResMap.has(RD.Reg)) {
+ if (!Eval || ResMap.count(RD.Reg) == 0) {
// Set to "ref" (aka "bottom").
uint16_t DefBW = ME.getRegBitWidth(RD);
RegisterCell RefC = RegisterCell::self(RD.Reg, DefBW);
@@ -1005,7 +1005,7 @@ void BT::put(RegisterRef RR, const RegisterCell &RC) {
// Replace all references to bits from OldRR with the corresponding bits
// in NewRR.
void BT::subst(RegisterRef OldRR, RegisterRef NewRR) {
- assert(Map.has(OldRR.Reg) && "OldRR not present in map");
+ assert(Map.count(OldRR.Reg) > 0 && "OldRR not present in map");
BitMask OM = ME.mask(OldRR.Reg, OldRR.Sub);
BitMask NM = ME.mask(NewRR.Reg, NewRR.Sub);
uint16_t OMB = OM.first(), OME = OM.last();
diff --git a/llvm/lib/Target/Hexagon/BitTracker.h b/llvm/lib/Target/Hexagon/BitTracker.h
index ed002a794d6..fd3a68f4385 100644
--- a/llvm/lib/Target/Hexagon/BitTracker.h
+++ b/llvm/lib/Target/Hexagon/BitTracker.h
@@ -36,9 +36,7 @@ struct BitTracker {
typedef SetVector<const MachineBasicBlock *> BranchTargetList;
- struct CellMapType : public std::map<unsigned,RegisterCell> {
- bool has(unsigned Reg) const;
- };
+ typedef std::map<unsigned, RegisterCell> CellMapType;
BitTracker(const MachineEvaluator &E, MachineFunction &F);
~BitTracker();
@@ -344,11 +342,6 @@ BitTracker::RegisterCell::ref(const RegisterCell &C) {
return RC;
}
-
-inline bool BitTracker::CellMapType::has(unsigned Reg) const {
- return find(Reg) != end();
-}
-
// A class to evaluate target's instructions and update the cell maps.
// This is used internally by the bit tracker. A target that wants to
// utilize this should implement the evaluation functions (noted below)
diff --git a/llvm/lib/Target/Hexagon/HexagonBitTracker.cpp b/llvm/lib/Target/Hexagon/HexagonBitTracker.cpp
index 021e58a1d08..15163d43fba 100644
--- a/llvm/lib/Target/Hexagon/HexagonBitTracker.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonBitTracker.cpp
@@ -95,30 +95,29 @@ BT::BitMask HexagonEvaluator::mask(unsigned Reg, unsigned Sub) const {
llvm_unreachable("Unexpected register/subregister");
}
-
namespace {
- struct RegisterRefs : public std::vector<BT::RegisterRef> {
- typedef std::vector<BT::RegisterRef> Base;
- RegisterRefs(const MachineInstr *MI);
- const BT::RegisterRef &operator[](unsigned n) const {
- // The main purpose of this operator is to assert with bad argument.
- assert(n < size());
- return Base::operator[](n);
- }
- };
+class RegisterRefs {
+ std::vector<BT::RegisterRef> Vector;
- RegisterRefs::RegisterRefs(const MachineInstr *MI)
- : Base(MI->getNumOperands()) {
- for (unsigned i = 0, n = size(); i < n; ++i) {
+public:
+ RegisterRefs(const MachineInstr *MI) : Vector(MI->getNumOperands()) {
+ for (unsigned i = 0, n = Vector.size(); i < n; ++i) {
const MachineOperand &MO = MI->getOperand(i);
if (MO.isReg())
- at(i) = BT::RegisterRef(MO);
+ Vector[i] = BT::RegisterRef(MO);
// For indices that don't correspond to registers, the entry will
// remain constructed via the default constructor.
}
}
-}
+ size_t size() const { return Vector.size(); }
+ const BT::RegisterRef &operator[](unsigned n) const {
+ // The main purpose of this operator is to assert with bad argument.
+ assert(n < Vector.size());
+ return Vector[n];
+ }
+};
+}
bool HexagonEvaluator::evaluate(const MachineInstr *MI,
const CellMapType &Inputs, CellMapType &Outputs) const {
diff --git a/llvm/lib/Target/Hexagon/HexagonCommonGEP.cpp b/llvm/lib/Target/Hexagon/HexagonCommonGEP.cpp
index 9f5fac15652..df6c17f27b2 100644
--- a/llvm/lib/Target/Hexagon/HexagonCommonGEP.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonCommonGEP.cpp
@@ -59,30 +59,23 @@ namespace {
// Numbering map for gep nodes. Used to keep track of ordering for
// gep nodes.
- struct NodeNumbering : public std::map<const GepNode*,unsigned> {
- };
-
- struct NodeOrdering : public NodeNumbering {
+ struct NodeOrdering {
NodeOrdering() : LastNum(0) {}
-#ifdef _MSC_VER
- void special_insert_for_special_msvc(const GepNode *N)
-#else
- using NodeNumbering::insert;
- void insert(const GepNode* N)
-#endif
- {
- insert(std::make_pair(N, ++LastNum));
- }
- bool operator() (const GepNode* N1, const GepNode *N2) const {
- const_iterator F1 = find(N1), F2 = find(N2);
- assert(F1 != end() && F2 != end());
+
+ void insert(const GepNode *N) { Map.insert(std::make_pair(N, ++LastNum)); }
+ void clear() { Map.clear(); }
+
+ bool operator()(const GepNode *N1, const GepNode *N2) const {
+ auto F1 = Map.find(N1), F2 = Map.find(N2);
+ assert(F1 != Map.end() && F2 != Map.end());
return F1->second < F2->second;
}
+
private:
+ std::map<const GepNode *, unsigned> Map;
unsigned LastNum;
};
-
class HexagonCommonGEP : public FunctionPass {
public:
static char ID;
@@ -360,11 +353,7 @@ void HexagonCommonGEP::processGepInst(GetElementPtrInst *GepI,
Us.insert(&UI.getUse());
}
Nodes.push_back(N);
-#ifdef _MSC_VER
- NodeOrder.special_insert_for_special_msvc(N);
-#else
NodeOrder.insert(N);
-#endif
// Skip the first index operand, since we only handle 0. This dereferences
// the pointer operand.
@@ -379,11 +368,7 @@ void HexagonCommonGEP::processGepInst(GetElementPtrInst *GepI,
Nx->PTy = PtrTy;
Nx->Idx = Op;
Nodes.push_back(Nx);
-#ifdef _MSC_VER
- NodeOrder.special_insert_for_special_msvc(Nx);
-#else
NodeOrder.insert(Nx);
-#endif
PN = Nx;
PtrTy = next_type(PtrTy, Op);
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