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-rw-r--r--llvm/lib/Target/RISCV/RISCVISelLowering.cpp11
-rw-r--r--llvm/test/CodeGen/RISCV/double-calling-conv.ll46
-rw-r--r--llvm/test/CodeGen/RISCV/double-imm.ll12
-rw-r--r--llvm/test/CodeGen/RISCV/double-previous-failure.ll18
4 files changed, 40 insertions, 47 deletions
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 12e07143b7b..18016541072 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -633,6 +633,17 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
return DCI.CombineTo(N, Op0.getOperand(0), Op0.getOperand(1));
SDLoc DL(N);
+
+ // It's cheaper to materialise two 32-bit integers than to load a double
+ // from the constant pool and transfer it to integer registers through the
+ // stack.
+ if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Op0)) {
+ APInt V = C->getValueAPF().bitcastToAPInt();
+ SDValue Lo = DAG.getConstant(V.trunc(32), DL, MVT::i32);
+ SDValue Hi = DAG.getConstant(V.lshr(32).trunc(32), DL, MVT::i32);
+ return DCI.CombineTo(N, Lo, Hi);
+ }
+
// This is a target-specific version of a DAGCombine performed in
// DAGCombiner::visitBITCAST. It performs the equivalent of:
// fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit)
diff --git a/llvm/test/CodeGen/RISCV/double-calling-conv.ll b/llvm/test/CodeGen/RISCV/double-calling-conv.ll
index 2fe79418922..f3cb0feb5f4 100644
--- a/llvm/test/CodeGen/RISCV/double-calling-conv.ll
+++ b/llvm/test/CodeGen/RISCV/double-calling-conv.ll
@@ -34,18 +34,13 @@ define double @caller_double_inreg() nounwind {
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp)
-; RV32IFD-NEXT: lui a0, %hi(.LCPI1_0)
-; RV32IFD-NEXT: addi a0, a0, %lo(.LCPI1_0)
-; RV32IFD-NEXT: fld ft0, 0(a0)
-; RV32IFD-NEXT: lui a0, %hi(.LCPI1_1)
-; RV32IFD-NEXT: addi a0, a0, %lo(.LCPI1_1)
-; RV32IFD-NEXT: fld ft1, 0(a0)
-; RV32IFD-NEXT: fsd ft1, 0(sp)
-; RV32IFD-NEXT: lw a0, 0(sp)
-; RV32IFD-NEXT: lw a1, 4(sp)
-; RV32IFD-NEXT: fsd ft0, 0(sp)
-; RV32IFD-NEXT: lw a2, 0(sp)
-; RV32IFD-NEXT: lw a3, 4(sp)
+; RV32IFD-NEXT: lui a0, 262236
+; RV32IFD-NEXT: addi a1, a0, 655
+; RV32IFD-NEXT: lui a0, 377487
+; RV32IFD-NEXT: addi a0, a0, 1475
+; RV32IFD-NEXT: lui a2, 262364
+; RV32IFD-NEXT: addi a3, a2, 655
+; RV32IFD-NEXT: mv a2, a0
; RV32IFD-NEXT: call callee_double_inreg
; RV32IFD-NEXT: lw ra, 12(sp)
; RV32IFD-NEXT: addi sp, sp, 16
@@ -78,29 +73,24 @@ define double @callee_double_split_reg_stack(i32 %a, i64 %b, i64 %c, double %d,
define double @caller_double_split_reg_stack() nounwind {
; RV32IFD-LABEL: caller_double_split_reg_stack:
; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: addi sp, sp, -32
-; RV32IFD-NEXT: sw ra, 28(sp)
-; RV32IFD-NEXT: lui a0, %hi(.LCPI3_0)
-; RV32IFD-NEXT: addi a0, a0, %lo(.LCPI3_0)
-; RV32IFD-NEXT: fld ft0, 0(a0)
-; RV32IFD-NEXT: fsd ft0, 16(sp)
-; RV32IFD-NEXT: lw a7, 16(sp)
-; RV32IFD-NEXT: lw a0, 20(sp)
+; RV32IFD-NEXT: addi sp, sp, -16
+; RV32IFD-NEXT: sw ra, 12(sp)
+; RV32IFD-NEXT: lui a0, 262510
+; RV32IFD-NEXT: addi a0, a0, 327
; RV32IFD-NEXT: sw a0, 0(sp)
-; RV32IFD-NEXT: lui a0, %hi(.LCPI3_1)
-; RV32IFD-NEXT: addi a0, a0, %lo(.LCPI3_1)
-; RV32IFD-NEXT: fld ft0, 0(a0)
-; RV32IFD-NEXT: fsd ft0, 16(sp)
-; RV32IFD-NEXT: lw a5, 16(sp)
-; RV32IFD-NEXT: lw a6, 20(sp)
+; RV32IFD-NEXT: lui a0, 262446
+; RV32IFD-NEXT: addi a6, a0, 327
+; RV32IFD-NEXT: lui a0, 713032
+; RV32IFD-NEXT: addi a5, a0, -1311
; RV32IFD-NEXT: addi a0, zero, 1
; RV32IFD-NEXT: addi a1, zero, 2
; RV32IFD-NEXT: mv a2, zero
; RV32IFD-NEXT: addi a3, zero, 3
; RV32IFD-NEXT: mv a4, zero
+; RV32IFD-NEXT: mv a7, a5
; RV32IFD-NEXT: call callee_double_split_reg_stack
-; RV32IFD-NEXT: lw ra, 28(sp)
-; RV32IFD-NEXT: addi sp, sp, 32
+; RV32IFD-NEXT: lw ra, 12(sp)
+; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
%1 = call double @callee_double_split_reg_stack(i32 1, i64 2, i64 3, double 4.72, double 5.72)
ret double %1
diff --git a/llvm/test/CodeGen/RISCV/double-imm.ll b/llvm/test/CodeGen/RISCV/double-imm.ll
index 8a763b82202..7f835644066 100644
--- a/llvm/test/CodeGen/RISCV/double-imm.ll
+++ b/llvm/test/CodeGen/RISCV/double-imm.ll
@@ -10,14 +10,10 @@ define double @double_imm() nounwind {
;
; RV32IFD-LABEL: double_imm:
; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: addi sp, sp, -16
-; RV32IFD-NEXT: lui a0, %hi(.LCPI0_0)
-; RV32IFD-NEXT: addi a0, a0, %lo(.LCPI0_0)
-; RV32IFD-NEXT: fld ft0, 0(a0)
-; RV32IFD-NEXT: fsd ft0, 8(sp)
-; RV32IFD-NEXT: lw a0, 8(sp)
-; RV32IFD-NEXT: lw a1, 12(sp)
-; RV32IFD-NEXT: addi sp, sp, 16
+; RV32IFD-NEXT: lui a0, 345155
+; RV32IFD-NEXT: addi a0, a0, -744
+; RV32IFD-NEXT: lui a1, 262290
+; RV32IFD-NEXT: addi a1, a1, 507
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: double_imm:
diff --git a/llvm/test/CodeGen/RISCV/double-previous-failure.ll b/llvm/test/CodeGen/RISCV/double-previous-failure.ll
index 3a07e5d5858..168c6c2e67d 100644
--- a/llvm/test/CodeGen/RISCV/double-previous-failure.ll
+++ b/llvm/test/CodeGen/RISCV/double-previous-failure.ll
@@ -17,24 +17,20 @@ define i32 @main() nounwind {
; RV32IFD: # %bb.0: # %entry
; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp)
-; RV32IFD-NEXT: lui a0, %hi(.LCPI1_0)
-; RV32IFD-NEXT: addi a0, a0, %lo(.LCPI1_0)
-; RV32IFD-NEXT: fld ft0, 0(a0)
-; RV32IFD-NEXT: fsd ft0, 0(sp)
-; RV32IFD-NEXT: lw a0, 0(sp)
-; RV32IFD-NEXT: lw a1, 4(sp)
+; RV32IFD-NEXT: mv a0, zero
+; RV32IFD-NEXT: lui a1, 262144
; RV32IFD-NEXT: call test
-; RV32IFD-NEXT: lui a2, %hi(.LCPI1_1)
-; RV32IFD-NEXT: addi a2, a2, %lo(.LCPI1_1)
-; RV32IFD-NEXT: fld ft1, 0(a2)
; RV32IFD-NEXT: sw a0, 0(sp)
; RV32IFD-NEXT: sw a1, 4(sp)
; RV32IFD-NEXT: fld ft0, 0(sp)
+; RV32IFD-NEXT: lui a0, %hi(.LCPI1_0)
+; RV32IFD-NEXT: addi a0, a0, %lo(.LCPI1_0)
+; RV32IFD-NEXT: fld ft1, 0(a0)
; RV32IFD-NEXT: flt.d a0, ft0, ft1
; RV32IFD-NEXT: bnez a0, .LBB1_3
; RV32IFD-NEXT: # %bb.1: # %entry
-; RV32IFD-NEXT: lui a0, %hi(.LCPI1_2)
-; RV32IFD-NEXT: addi a0, a0, %lo(.LCPI1_2)
+; RV32IFD-NEXT: lui a0, %hi(.LCPI1_1)
+; RV32IFD-NEXT: addi a0, a0, %lo(.LCPI1_1)
; RV32IFD-NEXT: fld ft1, 0(a0)
; RV32IFD-NEXT: flt.d a0, ft1, ft0
; RV32IFD-NEXT: xori a0, a0, 1
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