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-rw-r--r--llvm/lib/Target/AArch64/AArch64FastISel.cpp8
-rw-r--r--llvm/test/CodeGen/AArch64/fast-isel-sp-adjust.ll288
2 files changed, 296 insertions, 0 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64FastISel.cpp b/llvm/lib/Target/AArch64/AArch64FastISel.cpp
index e8fcf1a0e9b..7bf2097c17c 100644
--- a/llvm/lib/Target/AArch64/AArch64FastISel.cpp
+++ b/llvm/lib/Target/AArch64/AArch64FastISel.cpp
@@ -1282,6 +1282,10 @@ unsigned AArch64FastISel::emitAddSub_rr(bool UseAdd, MVT RetVT, unsigned LHSReg,
bool WantResult) {
assert(LHSReg && RHSReg && "Invalid register number.");
+ if (LHSReg == AArch64::SP || LHSReg == AArch64::WSP ||
+ RHSReg == AArch64::SP || RHSReg == AArch64::WSP)
+ return 0;
+
if (RetVT != MVT::i32 && RetVT != MVT::i64)
return 0;
@@ -1362,6 +1366,8 @@ unsigned AArch64FastISel::emitAddSub_rs(bool UseAdd, MVT RetVT, unsigned LHSReg,
uint64_t ShiftImm, bool SetFlags,
bool WantResult) {
assert(LHSReg && RHSReg && "Invalid register number.");
+ assert(LHSReg != AArch64::SP && LHSReg != AArch64::WSP &&
+ RHSReg != AArch64::SP && RHSReg != AArch64::WSP);
if (RetVT != MVT::i32 && RetVT != MVT::i64)
return 0;
@@ -1403,6 +1409,8 @@ unsigned AArch64FastISel::emitAddSub_rx(bool UseAdd, MVT RetVT, unsigned LHSReg,
uint64_t ShiftImm, bool SetFlags,
bool WantResult) {
assert(LHSReg && RHSReg && "Invalid register number.");
+ assert(LHSReg != AArch64::XZR && LHSReg != AArch64::WZR &&
+ RHSReg != AArch64::XZR && RHSReg != AArch64::WZR);
if (RetVT != MVT::i32 && RetVT != MVT::i64)
return 0;
diff --git a/llvm/test/CodeGen/AArch64/fast-isel-sp-adjust.ll b/llvm/test/CodeGen/AArch64/fast-isel-sp-adjust.ll
new file mode 100644
index 00000000000..9201d1be6a9
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/fast-isel-sp-adjust.ll
@@ -0,0 +1,288 @@
+; RUN: llc -O0 -mtriple=aarch64-apple-ios -o - %s | FileCheck %s
+; RUN: not llc -O0 -mtriple=aarch64-apple-ios -o /dev/null -fast-isel-abort=3 %s 2> %t
+; RUN: FileCheck %s --check-prefix=CHECK-ERRORS < %t
+
+; The issue here is that FastISel cannot emit an ADDrr where one of the inputs
+; is SP. This only ever crops up with function calls, and then only if the
+; argument is at an offset > 2^12 * size from SP.
+
+; If FastISel ever starts coping with this and emits an "add xD, sp, xM" it's
+; critical to check the encoding as well as the textual assembly. An ADDXrs with
+; SP as an operand will still print with SP, but will actually mean XZR.
+
+; CHECK-ERRORS: LLVM ERROR: FastISel missed call
+
+; CHECK-LABEL: foo:
+; CHECK-DAG: mov x[[SP:[0-9]+]], sp
+; CHECK-DAG: mov [[TMP:w[0-9]+]], #4104
+; CHECK: mov w[[OFFSET:[0-9]+]], [[TMP]]
+; CHECK: strb w0, [x[[SP]], x[[OFFSET]]]
+
+define void @foo(i8 %in) {
+ call void @bar(i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef, ; All regs gone.
+ i64 undef, i64 undef, i64 undef, i64 undef, ; sp + 32
+ i64 undef, i64 undef, i64 undef, i64 undef, ; sp + 64
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef, ; sp + 128
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef, ; sp + 256
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef, ; sp + 512
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef, ; sp + 1024
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef, ; sp + 2048
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef,
+ i64 undef, i64 undef, i64 undef, i64 undef, ; sp + 4096
+ i64 undef, ; sp + 4104 (i.e. not uimm12 or uimm12 << 12).
+ i8 %in)
+ ret void
+}
+
+declare void @bar(i64, i64, i64, i64,
+ i64, i64, i64, i64, ; All regs gone.
+ i64, i64, i64, i64, ; sp + 32
+ i64, i64, i64, i64, ; sp + 64
+ i64, i64, i64, i64,
+ i64, i64, i64, i64, ; sp + 128
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64, ; sp + 256
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64, ; sp + 512
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64, ; sp + 1024
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64, ; sp + 2048
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64,
+ i64, i64, i64, i64, ; sp + 4096
+ i64,
+ i8)
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