diff options
Diffstat (limited to 'llvm')
94 files changed, 323 insertions, 90 deletions
diff --git a/llvm/include/llvm/MC/MCAsmInfo.h b/llvm/include/llvm/MC/MCAsmInfo.h index b74ae846350..f039ba0db15 100644 --- a/llvm/include/llvm/MC/MCAsmInfo.h +++ b/llvm/include/llvm/MC/MCAsmInfo.h @@ -299,6 +299,14 @@ namespace llvm { std::vector<MCCFIInstruction> InitialFrameState; + //===--- Integrated Assembler State ----------------------------------===// + /// Should we use the integrated assembler? + /// The integrated assembler should be enabled by default (by the + /// constructors) when failing to parse a valid piece of assembly (inline + /// or otherwise) is considered a bug. It may then be overridden after + /// construction (see LLVMTargetMachine::initAsmInfo()). + bool UseIntegratedAssembler; + public: explicit MCAsmInfo(); virtual ~MCAsmInfo(); @@ -526,6 +534,14 @@ namespace llvm { const std::vector<MCCFIInstruction> &getInitialFrameState() const { return InitialFrameState; } + + /// Return true if assembly (inline or otherwise) should be parsed. + bool useIntegratedAssembler() const { return UseIntegratedAssembler; } + + /// Set whether assembly (inline or otherwise) should be parsed. + void setUseIntegratedAssembler(bool Value) { + UseIntegratedAssembler = Value; + } }; } diff --git a/llvm/include/llvm/MC/MCObjectStreamer.h b/llvm/include/llvm/MC/MCObjectStreamer.h index 18841979aba..66a2061957c 100644 --- a/llvm/include/llvm/MC/MCObjectStreamer.h +++ b/llvm/include/llvm/MC/MCObjectStreamer.h @@ -51,6 +51,9 @@ public: /// state management virtual void reset(); + /// Object streamers require the integrated assembler. + virtual bool isIntegratedAssemblerRequired() const { return true; } + protected: MCSectionData *getCurrentSectionData() const { return CurSectionData; diff --git a/llvm/include/llvm/MC/MCStreamer.h b/llvm/include/llvm/MC/MCStreamer.h index f2937187aaa..959fdbb5082 100644 --- a/llvm/include/llvm/MC/MCStreamer.h +++ b/llvm/include/llvm/MC/MCStreamer.h @@ -75,6 +75,8 @@ public: MCTargetStreamer(MCStreamer &S); virtual ~MCTargetStreamer(); + const MCStreamer &getStreamer() { return Streamer; } + // Allow a target to add behavior to the EmitLabel of MCStreamer. virtual void emitLabel(MCSymbol *Symbol); @@ -233,6 +235,10 @@ public: /// unformatted text to the .s file with EmitRawText. virtual bool hasRawTextSupport() const { return false; } + /// Is the integrated assembler required for this streamer to function + /// correctly? + virtual bool isIntegratedAssemblerRequired() const { return false; } + /// AddComment - Add a comment that can be emitted to the generated .s /// file if applicable as a QoI issue to make the output of the compiler /// more readable. This only affects the MCAsmStreamer, and only when diff --git a/llvm/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp b/llvm/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp index 8badf429d2d..f2813e72c1a 100644 --- a/llvm/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp @@ -79,10 +79,15 @@ void AsmPrinter::EmitInlineAsm(StringRef Str, const MDNode *LocMDNode, if (isNullTerminated) Str = Str.substr(0, Str.size()-1); - // If the output streamer is actually a .s file, just emit the blob textually. + // If the output streamer does not have mature MC support or the integrated + // assembler has been disabled, just emit the blob textually. + // Otherwise parse the asm and emit it via MC support. // This is useful in case the asm parser doesn't handle something but the // system assembler does. - if (OutStreamer.hasRawTextSupport()) { + const MCAsmInfo *MCAI = TM.getMCAsmInfo(); + assert(MCAI && "No MCAsmInfo"); + if (!MCAI->useIntegratedAssembler() && + !OutStreamer.isIntegratedAssemblerRequired()) { OutStreamer.EmitRawText(Str); emitInlineAsmEnd(TM.getSubtarget<MCSubtargetInfo>(), 0); return; diff --git a/llvm/lib/CodeGen/LLVMTargetMachine.cpp b/llvm/lib/CodeGen/LLVMTargetMachine.cpp index d897757ab71..51cd9d68617 100644 --- a/llvm/lib/CodeGen/LLVMTargetMachine.cpp +++ b/llvm/lib/CodeGen/LLVMTargetMachine.cpp @@ -53,6 +53,10 @@ static cl::opt<cl::boolOrDefault> AsmVerbose("asm-verbose", cl::desc("Add comments to directives."), cl::init(cl::BOU_UNSET)); +static cl::opt<bool> +NoIntegratedAssembler("no-integrated-as", cl::Hidden, + cl::desc("Disable integrated assembler")); + static bool getVerboseAsm() { switch (AsmVerbose) { case cl::BOU_UNSET: return TargetMachine::getAsmVerbosityDefault(); @@ -63,14 +67,20 @@ static bool getVerboseAsm() { } void LLVMTargetMachine::initAsmInfo() { - AsmInfo = TheTarget.createMCAsmInfo(*getRegisterInfo(), TargetTriple); + MCAsmInfo *TmpAsmInfo = TheTarget.createMCAsmInfo(*getRegisterInfo(), + TargetTriple); // TargetSelect.h moved to a different directory between LLVM 2.9 and 3.0, // and if the old one gets included then MCAsmInfo will be NULL and // we'll crash later. // Provide the user with a useful error message about what's wrong. - assert(AsmInfo && "MCAsmInfo not initialized. " + assert(TmpAsmInfo && "MCAsmInfo not initialized. " "Make sure you include the correct TargetSelect.h" "and that InitializeAllTargetMCs() is being invoked!"); + + if (NoIntegratedAssembler) + TmpAsmInfo->setUseIntegratedAssembler(false); + + AsmInfo = TmpAsmInfo; } LLVMTargetMachine::LLVMTargetMachine(const Target &T, StringRef Triple, diff --git a/llvm/lib/MC/MCAsmInfo.cpp b/llvm/lib/MC/MCAsmInfo.cpp index 7ece2729a92..0243f008fc9 100644 --- a/llvm/lib/MC/MCAsmInfo.cpp +++ b/llvm/lib/MC/MCAsmInfo.cpp @@ -86,6 +86,20 @@ MCAsmInfo::MCAsmInfo() { DwarfRegNumForCFI = false; NeedsDwarfSectionOffsetDirective = false; UseParensForSymbolVariant = false; + + // FIXME: Clang's logic should be synced with the logic used to initialize + // this member and the two implementations should be merged. + // For reference: + // - Solaris always enables the integrated assembler by default + // - SparcELFMCAsmInfo and X86ELFMCAsmInfo are handling this case + // - Windows always enables the integrated assembler by default + // - MCAsmInfoCOFF is handling this case, should it be MCAsmInfoMicrosoft? + // - MachO targets always enables the integrated assembler by default + // - MCAsmInfoDarwin is handling this case + // - Generic_GCC toolchains enable the integrated assembler on a per + // architecture basis. + // - The target subclasses for AArch64, ARM, and X86 handle these cases + UseIntegratedAssembler = false; } MCAsmInfo::~MCAsmInfo() { diff --git a/llvm/lib/MC/MCAsmInfoCOFF.cpp b/llvm/lib/MC/MCAsmInfoCOFF.cpp index f11227c6474..99456379f7b 100644 --- a/llvm/lib/MC/MCAsmInfoCOFF.cpp +++ b/llvm/lib/MC/MCAsmInfoCOFF.cpp @@ -35,6 +35,8 @@ MCAsmInfoCOFF::MCAsmInfoCOFF() { HasLEB128 = true; // Target asm supports leb128 directives (little-endian) SupportsDebugInformation = true; NeedsDwarfSectionOffsetDirective = true; + + UseIntegratedAssembler = true; } void MCAsmInfoMicrosoft::anchor() { } diff --git a/llvm/lib/MC/MCAsmInfoDarwin.cpp b/llvm/lib/MC/MCAsmInfoDarwin.cpp index d5382e69538..e907b751029 100644 --- a/llvm/lib/MC/MCAsmInfoDarwin.cpp +++ b/llvm/lib/MC/MCAsmInfoDarwin.cpp @@ -57,4 +57,6 @@ MCAsmInfoDarwin::MCAsmInfoDarwin() { HasNoDeadStrip = true; DwarfUsesRelocationsAcrossSections = false; + + UseIntegratedAssembler = true; } diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.cpp b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.cpp index e9747d68668..189d4eba81a 100644 --- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.cpp +++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.cpp @@ -35,6 +35,8 @@ AArch64ELFMCAsmInfo::AArch64ELFMCAsmInfo() { // Exceptions handling ExceptionsType = ExceptionHandling::DwarfCFI; + + UseIntegratedAssembler = true; } // Pin the vtable to this file. diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.cpp index 3c3df1ec6a4..4c5f21a0542 100644 --- a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.cpp +++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.cpp @@ -29,6 +29,8 @@ ARMMCAsmInfoDarwin::ARMMCAsmInfoDarwin() { // Exceptions handling ExceptionsType = ExceptionHandling::SjLj; + + UseIntegratedAssembler = true; } void ARMELFMCAsmInfo::anchor() { } @@ -50,4 +52,6 @@ ARMELFMCAsmInfo::ARMELFMCAsmInfo() { // foo(plt) instead of foo@plt UseParensForSymbolVariant = true; + + UseIntegratedAssembler = true; } diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.cpp b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.cpp index fcd22fa5daf..b30ca9e9ab2 100644 --- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.cpp +++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.cpp @@ -38,11 +38,13 @@ PPCMCAsmInfoDarwin::PPCMCAsmInfoDarwin(bool is64Bit, const Triple& T) { // rather than OS version if (T.isMacOSX() && T.isMacOSXVersionLT(10, 6)) HasWeakDefCanBeHiddenDirective = false; + + UseIntegratedAssembler = true; } void PPCLinuxMCAsmInfo::anchor() { } -PPCLinuxMCAsmInfo::PPCLinuxMCAsmInfo(bool is64Bit) { +PPCLinuxMCAsmInfo::PPCLinuxMCAsmInfo(bool is64Bit, const Triple& T) { if (is64Bit) { PointerSize = CalleeSaveStackSlotSize = 8; } @@ -71,5 +73,9 @@ PPCLinuxMCAsmInfo::PPCLinuxMCAsmInfo(bool is64Bit) { ZeroDirective = "\t.space\t"; Data64bitsDirective = is64Bit ? "\t.quad\t" : 0; AssemblerDialect = 1; // New-Style mnemonics. + + if (T.getOS() == llvm::Triple::FreeBSD || + (T.getOS() == llvm::Triple::NetBSD && !is64Bit)) + UseIntegratedAssembler = true; } diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.h b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.h index 6e6152eab39..cee2cb72a94 100644 --- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.h +++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.h @@ -29,7 +29,7 @@ class Triple; class PPCLinuxMCAsmInfo : public MCAsmInfoELF { virtual void anchor(); public: - explicit PPCLinuxMCAsmInfo(bool is64Bit); + explicit PPCLinuxMCAsmInfo(bool is64Bit, const Triple&); }; } // namespace llvm diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp index 57eb4facaa8..105c51151f9 100644 --- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp +++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp @@ -75,7 +75,7 @@ static MCAsmInfo *createPPCMCAsmInfo(const MCRegisterInfo &MRI, StringRef TT) { if (TheTriple.isOSDarwin()) MAI = new PPCMCAsmInfoDarwin(isPPC64, TheTriple); else - MAI = new PPCLinuxMCAsmInfo(isPPC64); + MAI = new PPCLinuxMCAsmInfo(isPPC64, TheTriple); // Initial state of the frame pointer is R1. unsigned Reg = isPPC64 ? PPC::X1 : PPC::R1; diff --git a/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.cpp b/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.cpp index c5948680472..ef5f8ce1558 100644 --- a/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.cpp +++ b/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.cpp @@ -42,6 +42,9 @@ SparcELFMCAsmInfo::SparcELFMCAsmInfo(StringRef TT) { SunStyleELFSectionSwitchSyntax = true; UsesELFSectionDirectiveForBSS = true; + + if (TheTriple.getOS() == llvm::Triple::Solaris) + UseIntegratedAssembler = true; } const MCExpr* diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86MCAsmInfo.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86MCAsmInfo.cpp index 7d935558721..65618046611 100644 --- a/llvm/lib/Target/X86/MCTargetDesc/X86MCAsmInfo.cpp +++ b/llvm/lib/Target/X86/MCTargetDesc/X86MCAsmInfo.cpp @@ -76,6 +76,8 @@ X86MCAsmInfoDarwin::X86MCAsmInfoDarwin(const Triple &T) { // version in use. From at least >= ld64-97.17 (Xcode 3.2.6) the abs-ified // FDE relocs may be used. DwarfFDESymbolsUseAbsDiff = T.isMacOSX() && !T.isMacOSXVersionLT(10, 6); + + UseIntegratedAssembler = true; } X86_64MCAsmInfoDarwin::X86_64MCAsmInfoDarwin(const Triple &Triple) @@ -114,6 +116,10 @@ X86ELFMCAsmInfo::X86ELFMCAsmInfo(const Triple &T) { if ((T.getOS() == Triple::OpenBSD || T.getOS() == Triple::Bitrig) && T.getArch() == Triple::x86) Data64bitsDirective = 0; + + // Always enable the integrated assembler by default. + // Clang also enabled it when the OS is Solaris but that is redundant here. + UseIntegratedAssembler = true; } const MCExpr * @@ -144,6 +150,8 @@ X86MCAsmInfoMicrosoft::X86MCAsmInfoMicrosoft(const Triple &Triple) { TextAlignFillValue = 0x90; AllowAtInName = true; + + UseIntegratedAssembler = true; } void X86MCAsmInfoGNUCOFF::anchor() { } @@ -158,4 +166,6 @@ X86MCAsmInfoGNUCOFF::X86MCAsmInfoGNUCOFF(const Triple &Triple) { // Exceptions handling ExceptionsType = ExceptionHandling::DwarfCFI; + + UseIntegratedAssembler = true; } diff --git a/llvm/test/CodeGen/AArch64/inline-asm-constraints.ll b/llvm/test/CodeGen/AArch64/inline-asm-constraints.ll index 18a3b37b41d..365453c5fec 100644 --- a/llvm/test/CodeGen/AArch64/inline-asm-constraints.ll +++ b/llvm/test/CodeGen/AArch64/inline-asm-constraints.ll @@ -1,4 +1,4 @@ -;RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s +;RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon -no-integrated-as < %s | FileCheck %s define i64 @test_inline_constraint_r(i64 %base, i32 %offset) { ; CHECK-LABEL: test_inline_constraint_r: diff --git a/llvm/test/CodeGen/AArch64/inline-asm-modifiers.ll b/llvm/test/CodeGen/AArch64/inline-asm-modifiers.ll index b7f4d3c57ba..cb66335b105 100644 --- a/llvm/test/CodeGen/AArch64/inline-asm-modifiers.ll +++ b/llvm/test/CodeGen/AArch64/inline-asm-modifiers.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=aarch64-none-linux-gnu -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=aarch64-none-linux-gnu -relocation-model=pic -no-integrated-as < %s | FileCheck %s @var_simple = hidden global i32 0 @var_got = global i32 0 diff --git a/llvm/test/CodeGen/AArch64/mature-mc-support.ll b/llvm/test/CodeGen/AArch64/mature-mc-support.ll new file mode 100644 index 00000000000..eb5eb3b4fdc --- /dev/null +++ b/llvm/test/CodeGen/AArch64/mature-mc-support.ll @@ -0,0 +1,12 @@ +; Test that inline assembly is parsed by the MC layer when MC support is mature +; (even when the output is assembly). + +; RUN: not llc -march=aarch64 < %s > /dev/null 2> %t1 +; RUN: FileCheck %s < %t1 + +; RUN: not llc -march=aarch64 -filetype=obj < %s > /dev/null 2> %t2 +; RUN: FileCheck %s < %t2 + +module asm " .this_directive_is_very_unlikely_to_exist" + +; CHECK: LLVM ERROR: Error parsing inline asm diff --git a/llvm/test/CodeGen/ARM/2009-04-06-AsmModifier.ll b/llvm/test/CodeGen/ARM/2009-04-06-AsmModifier.ll index 7342f69631e..a8ea6f007c7 100644 --- a/llvm/test/CodeGen/ARM/2009-04-06-AsmModifier.ll +++ b/llvm/test/CodeGen/ARM/2009-04-06-AsmModifier.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm | grep "swi 107" +; RUN: llc < %s -march=arm -no-integrated-as | grep "swi 107" define i32 @_swilseek(i32) nounwind { entry: diff --git a/llvm/test/CodeGen/ARM/arm-modifier.ll b/llvm/test/CodeGen/ARM/arm-modifier.ll index 85486427772..f943aea9e1d 100644 --- a/llvm/test/CodeGen/ARM/arm-modifier.ll +++ b/llvm/test/CodeGen/ARM/arm-modifier.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s +; RUN: llc < %s -march=arm -mattr=+vfp2 -no-integrated-as | FileCheck %s define i32 @foo(float %scale, float %scale2) nounwind { entry: diff --git a/llvm/test/CodeGen/ARM/crash-O0.ll b/llvm/test/CodeGen/ARM/crash-O0.ll index 8bce4e0097f..8855bb99aaf 100644 --- a/llvm/test/CodeGen/ARM/crash-O0.ll +++ b/llvm/test/CodeGen/ARM/crash-O0.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -O0 -relocation-model=pic -disable-fp-elim +; RUN: llc < %s -O0 -relocation-model=pic -disable-fp-elim -no-integrated-as target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64-n32" target triple = "armv6-apple-darwin10" diff --git a/llvm/test/CodeGen/ARM/inlineasm-64bit.ll b/llvm/test/CodeGen/ARM/inlineasm-64bit.ll index 683a0c4b7d3..d098a4383bc 100644 --- a/llvm/test/CodeGen/ARM/inlineasm-64bit.ll +++ b/llvm/test/CodeGen/ARM/inlineasm-64bit.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -O3 -mtriple=arm-linux-gnueabi | FileCheck %s -; RUN: llc -mtriple=thumbv7-none-linux-gnueabi -verify-machineinstrs < %s | FileCheck %s +; RUN: llc < %s -O3 -mtriple=arm-linux-gnueabi -no-integrated-as | FileCheck %s +; RUN: llc -mtriple=thumbv7-none-linux-gnueabi -verify-machineinstrs -no-integrated-as < %s | FileCheck %s ; check if regs are passing correctly define void @i64_write(i64* %p, i64 %val) nounwind { ; CHECK-LABEL: i64_write: diff --git a/llvm/test/CodeGen/ARM/inlineasm-imm-arm.ll b/llvm/test/CodeGen/ARM/inlineasm-imm-arm.ll index 45dfcf0b82a..908f093ae27 100644 --- a/llvm/test/CodeGen/ARM/inlineasm-imm-arm.ll +++ b/llvm/test/CodeGen/ARM/inlineasm-imm-arm.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm +; RUN: llc < %s -march=arm -no-integrated-as ; Test ARM-mode "I" constraint, for any Data Processing immediate. define i32 @testI(i32 %x) { diff --git a/llvm/test/CodeGen/ARM/inlineasm3.ll b/llvm/test/CodeGen/ARM/inlineasm3.ll index 5ee3247209a..8275cca950f 100644 --- a/llvm/test/CodeGen/ARM/inlineasm3.ll +++ b/llvm/test/CodeGen/ARM/inlineasm3.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -float-abi=soft -mattr=+neon,+v6t2 | FileCheck %s +; RUN: llc < %s -march=arm -float-abi=soft -mattr=+neon,+v6t2 -no-integrated-as | FileCheck %s ; Radar 7449043 %struct.int32x4_t = type { <4 x i32> } diff --git a/llvm/test/CodeGen/ARM/mature-mc-support.ll b/llvm/test/CodeGen/ARM/mature-mc-support.ll new file mode 100644 index 00000000000..468f52e413e --- /dev/null +++ b/llvm/test/CodeGen/ARM/mature-mc-support.ll @@ -0,0 +1,12 @@ +; Test that inline assembly is parsed by the MC layer when MC support is mature +; (even when the output is assembly). + +; RUN: not llc -march=arm < %s > /dev/null 2> %t1 +; RUN: FileCheck %s < %t1 + +; RUN: not llc -march=arm -filetype=obj < %s > /dev/null 2> %t2 +; RUN: FileCheck %s < %t2 + +module asm " .this_directive_is_very_unlikely_to_exist" + +; CHECK: LLVM ERROR: Error parsing inline asm diff --git a/llvm/test/CodeGen/ARM/mult-alt-generic-arm.ll b/llvm/test/CodeGen/ARM/mult-alt-generic-arm.ll index a8104db337f..05e9b0facd6 100644 --- a/llvm/test/CodeGen/ARM/mult-alt-generic-arm.ll +++ b/llvm/test/CodeGen/ARM/mult-alt-generic-arm.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm +; RUN: llc < %s -march=arm -no-integrated-as ; ModuleID = 'mult-alt-generic.c' target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32" target triple = "arm" diff --git a/llvm/test/CodeGen/ARM/subreg-remat.ll b/llvm/test/CodeGen/ARM/subreg-remat.ll index 1bc0315354c..d5abfc0af51 100644 --- a/llvm/test/CodeGen/ARM/subreg-remat.ll +++ b/llvm/test/CodeGen/ARM/subreg-remat.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -relocation-model=pic -disable-fp-elim -mcpu=cortex-a8 -pre-RA-sched=source | FileCheck %s +; RUN: llc < %s -relocation-model=pic -disable-fp-elim -mcpu=cortex-a8 -pre-RA-sched=source -no-integrated-as | FileCheck %s target triple = "thumbv7-apple-ios" ; <rdar://problem/10032939> ; diff --git a/llvm/test/CodeGen/Generic/2007-04-08-MultipleFrameIndices.ll b/llvm/test/CodeGen/Generic/2007-04-08-MultipleFrameIndices.ll index 339f0f71ed5..21c05f17a7c 100644 --- a/llvm/test/CodeGen/Generic/2007-04-08-MultipleFrameIndices.ll +++ b/llvm/test/CodeGen/Generic/2007-04-08-MultipleFrameIndices.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s +; RUN: llc -no-integrated-as < %s ; XFAIL: sparc-sun-solaris2 ; PR1308 ; PR1557 diff --git a/llvm/test/CodeGen/Generic/2007-04-27-InlineAsm-X-Dest.ll b/llvm/test/CodeGen/Generic/2007-04-27-InlineAsm-X-Dest.ll index af522dc4c58..0f82ba61b28 100644 --- a/llvm/test/CodeGen/Generic/2007-04-27-InlineAsm-X-Dest.ll +++ b/llvm/test/CodeGen/Generic/2007-04-27-InlineAsm-X-Dest.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s +; RUN: llc -no-integrated-as < %s ; Test that we can have an "X" output constraint. diff --git a/llvm/test/CodeGen/Generic/2007-04-27-LargeMemObject.ll b/llvm/test/CodeGen/Generic/2007-04-27-LargeMemObject.ll index f2c9b7f849b..05989a0836c 100644 --- a/llvm/test/CodeGen/Generic/2007-04-27-LargeMemObject.ll +++ b/llvm/test/CodeGen/Generic/2007-04-27-LargeMemObject.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s +; RUN: llc -no-integrated-as < %s %struct..0anon = type { [100 x i32] } diff --git a/llvm/test/CodeGen/Generic/2007-12-17-InvokeAsm.ll b/llvm/test/CodeGen/Generic/2007-12-17-InvokeAsm.ll index 27c716222ef..03ccbdfaf0c 100644 --- a/llvm/test/CodeGen/Generic/2007-12-17-InvokeAsm.ll +++ b/llvm/test/CodeGen/Generic/2007-12-17-InvokeAsm.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s +; RUN: llc -no-integrated-as < %s define fastcc void @bc__support__high_resolution_time__initialize_clock_rate() { entry: diff --git a/llvm/test/CodeGen/Generic/2008-02-20-MatchingMem.ll b/llvm/test/CodeGen/Generic/2008-02-20-MatchingMem.ll index 7ffb734c713..5ddb515bb75 100644 --- a/llvm/test/CodeGen/Generic/2008-02-20-MatchingMem.ll +++ b/llvm/test/CodeGen/Generic/2008-02-20-MatchingMem.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s +; RUN: llc -no-integrated-as < %s ; PR1133 ; XFAIL: hexagon define void @test(i32* %X) nounwind { diff --git a/llvm/test/CodeGen/Generic/asm-large-immediate.ll b/llvm/test/CodeGen/Generic/asm-large-immediate.ll index 891bbc9cc16..67a7a1e75a8 100644 --- a/llvm/test/CodeGen/Generic/asm-large-immediate.ll +++ b/llvm/test/CodeGen/Generic/asm-large-immediate.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s | FileCheck %s +; RUN: llc -no-integrated-as < %s | FileCheck %s define void @test() { entry: diff --git a/llvm/test/CodeGen/Generic/inline-asm-mem-clobber.ll b/llvm/test/CodeGen/Generic/inline-asm-mem-clobber.ll index e523d031dc6..5aa827a0ab8 100644 --- a/llvm/test/CodeGen/Generic/inline-asm-mem-clobber.ll +++ b/llvm/test/CodeGen/Generic/inline-asm-mem-clobber.ll @@ -1,4 +1,4 @@ -; RUN: llc -O2 < %s | FileCheck %s +; RUN: llc -O2 -no-integrated-as < %s | FileCheck %s @G = common global i32 0, align 4 diff --git a/llvm/test/CodeGen/Generic/inline-asm-special-strings.ll b/llvm/test/CodeGen/Generic/inline-asm-special-strings.ll index d18221ef934..5ef568863ba 100644 --- a/llvm/test/CodeGen/Generic/inline-asm-special-strings.ll +++ b/llvm/test/CodeGen/Generic/inline-asm-special-strings.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s | grep "foo 0 0" +; RUN: llc -no-integrated-as < %s | grep "foo 0 0" define void @bar() nounwind { tail call void asm sideeffect "foo ${:uid} ${:uid}", ""() nounwind diff --git a/llvm/test/CodeGen/Mips/mature-mc-support.ll b/llvm/test/CodeGen/Mips/mature-mc-support.ll new file mode 100644 index 00000000000..6e5998d8a7c --- /dev/null +++ b/llvm/test/CodeGen/Mips/mature-mc-support.ll @@ -0,0 +1,32 @@ +; Test that inline assembly is parsed by the MC layer when MC support is mature +; (even when the output is assembly). +; FIXME: Mips doesn't use the integrated assembler by default so we only test +; that -filetype=obj tries to parse the assembly. + +; SKIP: not llc -march=mips < %s > /dev/null 2> %t1 +; SKIP: FileCheck %s < %t1 + +; RUN: not llc -march=mips -filetype=obj < %s > /dev/null 2> %t2 +; RUN: FileCheck %s < %t2 + +; SKIP: not llc -march=mipsel < %s > /dev/null 2> %t3 +; SKIP: FileCheck %s < %t3 + +; RUN: not llc -march=mipsel -filetype=obj < %s > /dev/null 2> %t4 +; RUN: FileCheck %s < %t4 + +; SKIP: not llc -march=mips64 < %s > /dev/null 2> %t5 +; SKIP: FileCheck %s < %t5 + +; RUN: not llc -march=mips64 -filetype=obj < %s > /dev/null 2> %t6 +; RUN: FileCheck %s < %t6 + +; SKIP: not llc -march=mips64el < %s > /dev/null 2> %t7 +; SKIP: FileCheck %s < %t7 + +; RUN: not llc -march=mips64el -filetype=obj < %s > /dev/null 2> %t8 +; RUN: FileCheck %s < %t8 + +module asm " .this_directive_is_very_unlikely_to_exist" + +; CHECK: LLVM ERROR: Error parsing inline asm diff --git a/llvm/test/CodeGen/PowerPC/2007-04-24-InlineAsm-I-Modifier.ll b/llvm/test/CodeGen/PowerPC/2007-04-24-InlineAsm-I-Modifier.ll index 73736c57fea..5eb6e375747 100644 --- a/llvm/test/CodeGen/PowerPC/2007-04-24-InlineAsm-I-Modifier.ll +++ b/llvm/test/CodeGen/PowerPC/2007-04-24-InlineAsm-I-Modifier.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8.8.0 | grep "foo r3, r4" -; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8.8.0 | grep "bari r3, 47" +; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8.8.0 -no-integrated-as | grep "foo r3, r4" +; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8.8.0 -no-integrated-as | grep "bari r3, 47" ; PR1351 diff --git a/llvm/test/CodeGen/PowerPC/2007-05-03-InlineAsm-S-Constraint.ll b/llvm/test/CodeGen/PowerPC/2007-05-03-InlineAsm-S-Constraint.ll index 1df51406fac..490aa0c1442 100644 --- a/llvm/test/CodeGen/PowerPC/2007-05-03-InlineAsm-S-Constraint.ll +++ b/llvm/test/CodeGen/PowerPC/2007-05-03-InlineAsm-S-Constraint.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s +; RUN: llc -no-integrated-as < %s ; PR1382 target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64" diff --git a/llvm/test/CodeGen/PowerPC/mature-mc-support.ll b/llvm/test/CodeGen/PowerPC/mature-mc-support.ll new file mode 100644 index 00000000000..7c83e184a6f --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/mature-mc-support.ll @@ -0,0 +1,27 @@ +; Test that inline assembly is parsed by the MC layer when MC support is mature +; (even when the output is assembly). +; FIXME: PowerPC doesn't use the integrated assembler by default in all cases +; so we only test that -filetype=obj tries to parse the assembly. +; FIXME: PowerPC doesn't appear to support -filetype=obj for ppc64le + +; SKIP: not llc -march=ppc32 < %s > /dev/null 2> %t1 +; SKIP: FileCheck %s < %t1 + +; RUN: not llc -march=ppc32 -filetype=obj < %s > /dev/null 2> %t2 +; RUN: FileCheck %s < %t2 + +; SKIP: not llc -march=ppc64 < %s > /dev/null 2> %t3 +; SKIP: FileCheck %s < %t3 + +; RUN: not llc -march=ppc64 -filetype=obj < %s > /dev/null 2> %t4 +; RUN: FileCheck %s < %t4 + +; SKIP: not llc -march=ppc64le < %s > /dev/null 2> %t5 +; SKIP: FileCheck %s < %t5 + +; SKIP: not llc -march=ppc64le -filetype=obj < %s > /dev/null 2> %t6 +; SKIP: FileCheck %s < %t6 + +module asm " .this_directive_is_very_unlikely_to_exist" + +; CHECK: LLVM ERROR: Error parsing inline asm diff --git a/llvm/test/CodeGen/SPARC/mature-mc-support.ll b/llvm/test/CodeGen/SPARC/mature-mc-support.ll new file mode 100644 index 00000000000..c4f8f8dd022 --- /dev/null +++ b/llvm/test/CodeGen/SPARC/mature-mc-support.ll @@ -0,0 +1,22 @@ +; Test that inline assembly is parsed by the MC layer when MC support is mature +; (even when the output is assembly). +; FIXME: SPARC doesn't use the integrated assembler by default in all cases +; so we only test that -filetype=obj tries to parse the assembly. +; FIXME: SPARC seems to accept directives that don't exist +; XFAIL: * + +; SKIP: not llc -march=sparc < %s > /dev/null 2> %t1 +; SKIP: FileCheck %s < %t1 + +; RUN: not llc -march=sparc -filetype=obj < %s > /dev/null 2> %t2 +; RUN: FileCheck %s < %t2 + +; SKIP: not llc -march=sparcv9 < %s > /dev/null 2> %t3 +; SKIP: FileCheck %s < %t3 + +; RUN: not llc -march=sparcv9 -filetype=obj < %s > /dev/null 2> %t4 +; RUN: FileCheck %s < %t4 + +module asm " .this_directive_is_very_unlikely_to_exist" + +; CHECK: LLVM ERROR: Error parsing inline asm diff --git a/llvm/test/CodeGen/SystemZ/mature-mc-support.ll b/llvm/test/CodeGen/SystemZ/mature-mc-support.ll new file mode 100644 index 00000000000..5520f55e1e2 --- /dev/null +++ b/llvm/test/CodeGen/SystemZ/mature-mc-support.ll @@ -0,0 +1,15 @@ +; Test that inline assembly is parsed by the MC layer when MC support is mature +; (even when the output is assembly). +; FIXME: SystemZ doesn't use the integrated assembler by default so we only test +; that -filetype=obj tries to parse the assembly. + +; SKIP: not llc -march=systemz < %s > /dev/null 2> %t1 +; SKIP: FileCheck %s < %t1 + +; RUN: not llc -march=systemz -filetype=obj < %s > /dev/null 2> %t2 +; RUN: FileCheck %s < %t2 + + +module asm " .this_directive_is_very_unlikely_to_exist" + +; CHECK: LLVM ERROR: Error parsing inline asm diff --git a/llvm/test/CodeGen/Thumb/inlineasm-imm-thumb.ll b/llvm/test/CodeGen/Thumb/inlineasm-imm-thumb.ll index 5c8a52af59e..d557b9d5a1f 100644 --- a/llvm/test/CodeGen/Thumb/inlineasm-imm-thumb.ll +++ b/llvm/test/CodeGen/Thumb/inlineasm-imm-thumb.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=thumb +; RUN: llc < %s -march=thumb -no-integrated-as ; Test Thumb-mode "I" constraint, for ADD immediate. define i32 @testI(i32 %x) { diff --git a/llvm/test/CodeGen/Thumb/mature-mc-support.ll b/llvm/test/CodeGen/Thumb/mature-mc-support.ll new file mode 100644 index 00000000000..d5e82538dd1 --- /dev/null +++ b/llvm/test/CodeGen/Thumb/mature-mc-support.ll @@ -0,0 +1,12 @@ +; Test that inline assembly is parsed by the MC layer when MC support is mature +; (even when the output is assembly). + +; RUN: not llc -march=thumb < %s > /dev/null 2> %t1 +; RUN: FileCheck %s < %t1 + +; RUN: not llc -march=thumb -filetype=obj < %s > /dev/null 2> %t2 +; RUN: FileCheck %s < %t2 + +module asm " .this_directive_is_very_unlikely_to_exist" + +; CHECK: LLVM ERROR: Error parsing inline asm diff --git a/llvm/test/CodeGen/X86/2006-07-20-InlineAsm.ll b/llvm/test/CodeGen/X86/2006-07-20-InlineAsm.ll index cac47cdab6d..1facf15b9f4 100644 --- a/llvm/test/CodeGen/X86/2006-07-20-InlineAsm.ll +++ b/llvm/test/CodeGen/X86/2006-07-20-InlineAsm.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 +; RUN: llc < %s -march=x86 -no-integrated-as ; PR833 @G = weak global i32 0 ; <i32*> [#uses=3] diff --git a/llvm/test/CodeGen/X86/2006-07-31-SingleRegClass.ll b/llvm/test/CodeGen/X86/2006-07-31-SingleRegClass.ll index c4b08a3be28..2a9c8324d36 100644 --- a/llvm/test/CodeGen/X86/2006-07-31-SingleRegClass.ll +++ b/llvm/test/CodeGen/X86/2006-07-31-SingleRegClass.ll @@ -1,5 +1,5 @@ ; PR850 -; RUN: llc < %s -march=x86 -x86-asm-syntax=att | FileCheck %s +; RUN: llc < %s -march=x86 -x86-asm-syntax=att -no-integrated-as | FileCheck %s ; CHECK: {{movl 4[(]%eax[)],%ebp}} ; CHECK: {{movl 0[(]%eax[)], %ebx}} diff --git a/llvm/test/CodeGen/X86/2007-03-24-InlineAsmPModifier.ll b/llvm/test/CodeGen/X86/2007-03-24-InlineAsmPModifier.ll index 3b2e443d7d4..93fb344cbb1 100644 --- a/llvm/test/CodeGen/X86/2007-03-24-InlineAsmPModifier.ll +++ b/llvm/test/CodeGen/X86/2007-03-24-InlineAsmPModifier.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 | grep "mov %gs:72, %eax" +; RUN: llc < %s -march=x86 -no-integrated-as | grep "mov %gs:72, %eax" target datalayout = "e-p:32:32" target triple = "i686-apple-darwin9" diff --git a/llvm/test/CodeGen/X86/2007-03-24-InlineAsmVectorOp.ll b/llvm/test/CodeGen/X86/2007-03-24-InlineAsmVectorOp.ll index 366f5830392..6cf8bf90611 100644 --- a/llvm/test/CodeGen/X86/2007-03-24-InlineAsmVectorOp.ll +++ b/llvm/test/CodeGen/X86/2007-03-24-InlineAsmVectorOp.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mcpu=yonah -march=x86 | FileCheck %s +; RUN: llc < %s -mcpu=yonah -march=x86 -no-integrated-as | FileCheck %s target datalayout = "e-p:32:32" target triple = "i686-apple-darwin9" diff --git a/llvm/test/CodeGen/X86/2007-10-28-inlineasm-q-modifier.ll b/llvm/test/CodeGen/X86/2007-10-28-inlineasm-q-modifier.ll index 984094d86a2..d02346d103c 100644 --- a/llvm/test/CodeGen/X86/2007-10-28-inlineasm-q-modifier.ll +++ b/llvm/test/CodeGen/X86/2007-10-28-inlineasm-q-modifier.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s +; RUN: llc -no-integrated-as < %s ; PR1748 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" target triple = "x86_64-unknown-linux-gnu" diff --git a/llvm/test/CodeGen/X86/2007-11-04-LiveVariablesBug.ll b/llvm/test/CodeGen/X86/2007-11-04-LiveVariablesBug.ll index 6b871aa3a4d..ec3bce9c666 100644 --- a/llvm/test/CodeGen/X86/2007-11-04-LiveVariablesBug.ll +++ b/llvm/test/CodeGen/X86/2007-11-04-LiveVariablesBug.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu +; RUN: llc -no-integrated-as < %s -mtriple=x86_64-unknown-linux-gnu ; PR1767 define void @xor_sse_2(i64 %bytes, i64* %p1, i64* %p2) { diff --git a/llvm/test/CodeGen/X86/2007-11-04-rip-immediate-constant.ll b/llvm/test/CodeGen/X86/2007-11-04-rip-immediate-constant.ll index c4670242b53..d1699d55711 100644 --- a/llvm/test/CodeGen/X86/2007-11-04-rip-immediate-constant.ll +++ b/llvm/test/CodeGen/X86/2007-11-04-rip-immediate-constant.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -relocation-model=static | FileCheck %s +; RUN: llc < %s -relocation-model=static -no-integrated-as | FileCheck %s ; PR1761 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" target triple = "x86_64-pc-linux" diff --git a/llvm/test/CodeGen/X86/2008-02-20-InlineAsmClobber.ll b/llvm/test/CodeGen/X86/2008-02-20-InlineAsmClobber.ll index b06b249a632..319e884139a 100644 --- a/llvm/test/CodeGen/X86/2008-02-20-InlineAsmClobber.ll +++ b/llvm/test/CodeGen/X86/2008-02-20-InlineAsmClobber.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s | FileCheck %s +; RUN: llc -no-integrated-as < %s | FileCheck %s ; PR2078 ; The clobber list says that "ax" is clobbered. Make sure that eax isn't ; allocated to the input/output register. diff --git a/llvm/test/CodeGen/X86/2008-02-26-AsmDirectMemOp.ll b/llvm/test/CodeGen/X86/2008-02-26-AsmDirectMemOp.ll index 0b4eb3a3b9b..11b55a6e5ac 100644 --- a/llvm/test/CodeGen/X86/2008-02-26-AsmDirectMemOp.ll +++ b/llvm/test/CodeGen/X86/2008-02-26-AsmDirectMemOp.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 +; RUN: llc < %s -march=x86 -no-integrated-as target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32" target triple = "i386-pc-linux-gnu" diff --git a/llvm/test/CodeGen/X86/2008-04-26-Asm-Optimize-Imm.ll b/llvm/test/CodeGen/X86/2008-04-26-Asm-Optimize-Imm.ll index d4805b4bb63..6d45f1f0030 100644 --- a/llvm/test/CodeGen/X86/2008-04-26-Asm-Optimize-Imm.ll +++ b/llvm/test/CodeGen/X86/2008-04-26-Asm-Optimize-Imm.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s | FileCheck %s +; RUN: llc -no-integrated-as < %s | FileCheck %s ; rdar://5720231 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" target triple = "i386-apple-darwin8" diff --git a/llvm/test/CodeGen/X86/2008-09-18-inline-asm-2.ll b/llvm/test/CodeGen/X86/2008-09-18-inline-asm-2.ll index 5c2fbeee5c7..f4a43a1e978 100644 --- a/llvm/test/CodeGen/X86/2008-09-18-inline-asm-2.ll +++ b/llvm/test/CodeGen/X86/2008-09-18-inline-asm-2.ll @@ -1,6 +1,6 @@ -; RUN: llc < %s -march=x86 -regalloc=fast -optimize-regalloc=0 | FileCheck %s -; RUN: llc < %s -march=x86 -regalloc=basic | FileCheck %s -; RUN: llc < %s -march=x86 -regalloc=greedy | FileCheck %s +; RUN: llc < %s -march=x86 -regalloc=fast -optimize-regalloc=0 -no-integrated-as | FileCheck %s +; RUN: llc < %s -march=x86 -regalloc=basic -no-integrated-as | FileCheck %s +; RUN: llc < %s -march=x86 -regalloc=greedy -no-integrated-as | FileCheck %s ; The 1st, 2nd, 3rd and 5th registers must all be different. The registers ; referenced in the 4th and 6th operands must not be the same as the 1st or 5th diff --git a/llvm/test/CodeGen/X86/2008-10-17-Asm64bitRConstraint.ll b/llvm/test/CodeGen/X86/2008-10-17-Asm64bitRConstraint.ll index b2e6061ff91..2b2f704349b 100644 --- a/llvm/test/CodeGen/X86/2008-10-17-Asm64bitRConstraint.ll +++ b/llvm/test/CodeGen/X86/2008-10-17-Asm64bitRConstraint.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -march=x86 -; RUN: llc < %s -march=x86-64 +; RUN: llc < %s -march=x86 -no-integrated-as +; RUN: llc < %s -march=x86-64 -no-integrated-as define void @test(i64 %x) nounwind { entry: diff --git a/llvm/test/CodeGen/X86/2008-10-20-AsmDoubleInI32.ll b/llvm/test/CodeGen/X86/2008-10-20-AsmDoubleInI32.ll index 353d1c75216..e23dfe5a6a1 100644 --- a/llvm/test/CodeGen/X86/2008-10-20-AsmDoubleInI32.ll +++ b/llvm/test/CodeGen/X86/2008-10-20-AsmDoubleInI32.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -march=x86 -; RUN: llc < %s -march=x86-64 +; RUN: llc < %s -march=x86 -no-integrated-as +; RUN: llc < %s -march=x86-64 -no-integrated-as ; from gcc.c-torture/compile/920520-1.c diff --git a/llvm/test/CodeGen/X86/2009-02-12-InlineAsm-nieZ-constraints.ll b/llvm/test/CodeGen/X86/2009-02-12-InlineAsm-nieZ-constraints.ll index 75496518afa..5004f04bf8f 100644 --- a/llvm/test/CodeGen/X86/2009-02-12-InlineAsm-nieZ-constraints.ll +++ b/llvm/test/CodeGen/X86/2009-02-12-InlineAsm-nieZ-constraints.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 | FileCheck %s +; RUN: llc < %s -march=x86 -no-integrated-as | FileCheck %s ; ModuleID = 'shant.c' target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" diff --git a/llvm/test/CodeGen/X86/2009-04-13-2AddrAssert-2.ll b/llvm/test/CodeGen/X86/2009-04-13-2AddrAssert-2.ll index 3d70b58686b..bd1b47a588e 100644 --- a/llvm/test/CodeGen/X86/2009-04-13-2AddrAssert-2.ll +++ b/llvm/test/CodeGen/X86/2009-04-13-2AddrAssert-2.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=i386-apple-darwin +; RUN: llc < %s -mtriple=i386-apple-darwin -no-integrated-as ; rdar://6781755 ; PR3934 diff --git a/llvm/test/CodeGen/X86/2009-05-08-InlineAsmIOffset.ll b/llvm/test/CodeGen/X86/2009-05-08-InlineAsmIOffset.ll index 7468acb95f1..fa240f64c30 100644 --- a/llvm/test/CodeGen/X86/2009-05-08-InlineAsmIOffset.ll +++ b/llvm/test/CodeGen/X86/2009-05-08-InlineAsmIOffset.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -relocation-model=static | FileCheck %s +; RUN: llc < %s -relocation-model=static -no-integrated-as | FileCheck %s ; PR4152 ; CHECK: {{1: ._pv_cpu_ops[+]8}} diff --git a/llvm/test/CodeGen/X86/2009-09-19-earlyclobber.ll b/llvm/test/CodeGen/X86/2009-09-19-earlyclobber.ll index 66f51180509..7df62fd8c37 100644 --- a/llvm/test/CodeGen/X86/2009-09-19-earlyclobber.ll +++ b/llvm/test/CodeGen/X86/2009-09-19-earlyclobber.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s | FileCheck %s +; RUN: llc -no-integrated-as < %s | FileCheck %s ; ModuleID = '4964.c' ; PR 4964 ; Registers other than RAX, RCX are OK, but they must be different. diff --git a/llvm/test/CodeGen/X86/2009-12-01-EarlyClobberBug.ll b/llvm/test/CodeGen/X86/2009-12-01-EarlyClobberBug.ll index b1664470551..5c10c55ea3e 100644 --- a/llvm/test/CodeGen/X86/2009-12-01-EarlyClobberBug.ll +++ b/llvm/test/CodeGen/X86/2009-12-01-EarlyClobberBug.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-apple-darwin -no-integrated-as | FileCheck %s ; pr5391 define void @t() nounwind ssp { diff --git a/llvm/test/CodeGen/X86/2010-05-05-LocalAllocEarlyClobber.ll b/llvm/test/CodeGen/X86/2010-05-05-LocalAllocEarlyClobber.ll index 74a5ec28db1..fc8c895af5b 100644 --- a/llvm/test/CodeGen/X86/2010-05-05-LocalAllocEarlyClobber.ll +++ b/llvm/test/CodeGen/X86/2010-05-05-LocalAllocEarlyClobber.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -O0 -regalloc=fast | FileCheck %s +; RUN: llc < %s -O0 -regalloc=fast -no-integrated-as | FileCheck %s ; PR6520 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n8:16:32" diff --git a/llvm/test/CodeGen/X86/2010-06-15-FastAllocEarlyCLobber.ll b/llvm/test/CodeGen/X86/2010-06-15-FastAllocEarlyCLobber.ll index 9b47bb75bf1..0f8855d1267 100644 --- a/llvm/test/CodeGen/X86/2010-06-15-FastAllocEarlyCLobber.ll +++ b/llvm/test/CodeGen/X86/2010-06-15-FastAllocEarlyCLobber.ll @@ -1,4 +1,4 @@ -; RUN: llc -regalloc=fast -optimize-regalloc=0 < %s | FileCheck %s +; RUN: llc -regalloc=fast -optimize-regalloc=0 -no-integrated-as < %s | FileCheck %s ; PR7382 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" target triple = "x86_64-unknown-linux-gnu" diff --git a/llvm/test/CodeGen/X86/2010-06-25-asm-RA-crash.ll b/llvm/test/CodeGen/X86/2010-06-25-asm-RA-crash.ll index 68a6a134de5..0df9dc1cb76 100644 --- a/llvm/test/CodeGen/X86/2010-06-25-asm-RA-crash.ll +++ b/llvm/test/CodeGen/X86/2010-06-25-asm-RA-crash.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -disable-fp-elim -mtriple=i686-pc-mingw32 +; RUN: llc < %s -disable-fp-elim -mtriple=i686-pc-mingw32 -no-integrated-as %struct.__SEH2Frame = type {} diff --git a/llvm/test/CodeGen/X86/2010-06-28-FastAllocTiedOperand.ll b/llvm/test/CodeGen/X86/2010-06-28-FastAllocTiedOperand.ll index e1491a03d8a..d7bc21f6393 100644 --- a/llvm/test/CodeGen/X86/2010-06-28-FastAllocTiedOperand.ll +++ b/llvm/test/CodeGen/X86/2010-06-28-FastAllocTiedOperand.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 -O0 | FileCheck %s +; RUN: llc < %s -march=x86 -O0 -no-integrated-as | FileCheck %s ; PR7509 target triple = "i386-apple-darwin10" %asmtype = type { i32, i8*, i32, i32 } diff --git a/llvm/test/CodeGen/X86/2010-06-28-matched-g-constraint.ll b/llvm/test/CodeGen/X86/2010-06-28-matched-g-constraint.ll index 82dac9d9930..a0798ae10d7 100644 --- a/llvm/test/CodeGen/X86/2010-06-28-matched-g-constraint.ll +++ b/llvm/test/CodeGen/X86/2010-06-28-matched-g-constraint.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=x86_64-apple-darwin11 | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-apple-darwin11 -no-integrated-as | FileCheck %s ; Any register is OK for %0, but it must be a register, not memory. define i32 @foo() nounwind ssp { diff --git a/llvm/test/CodeGen/X86/2010-07-02-asm-alignstack.ll b/llvm/test/CodeGen/X86/2010-07-02-asm-alignstack.ll index 0bbb24f6ecd..4302adda515 100644 --- a/llvm/test/CodeGen/X86/2010-07-02-asm-alignstack.ll +++ b/llvm/test/CodeGen/X86/2010-07-02-asm-alignstack.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=x86_64-apple-darwin10 | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -no-integrated-as | FileCheck %s define void @foo() nounwind ssp { entry: diff --git a/llvm/test/CodeGen/X86/2010-07-06-asm-RIP.ll b/llvm/test/CodeGen/X86/2010-07-06-asm-RIP.ll index 9526b8d4cdc..818bbc6a5bc 100644 --- a/llvm/test/CodeGen/X86/2010-07-06-asm-RIP.ll +++ b/llvm/test/CodeGen/X86/2010-07-06-asm-RIP.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-apple-darwin -no-integrated-as | FileCheck %s ; PR 4752 @n = global i32 0 ; <i32*> [#uses=2] diff --git a/llvm/test/CodeGen/X86/2010-07-13-indirectXconstraint.ll b/llvm/test/CodeGen/X86/2010-07-13-indirectXconstraint.ll index 97cbe3ea5a0..306e22ae5f1 100644 --- a/llvm/test/CodeGen/X86/2010-07-13-indirectXconstraint.ll +++ b/llvm/test/CodeGen/X86/2010-07-13-indirectXconstraint.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-apple-darwin -no-integrated-as | FileCheck %s ; PR 7528 ; formerly crashed diff --git a/llvm/test/CodeGen/X86/2011-10-11-SpillDead.ll b/llvm/test/CodeGen/X86/2011-10-11-SpillDead.ll index 8e70d6543ac..19c3d6ca727 100644 --- a/llvm/test/CodeGen/X86/2011-10-11-SpillDead.ll +++ b/llvm/test/CodeGen/X86/2011-10-11-SpillDead.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -verify-regalloc +; RUN: llc < %s -verify-regalloc -no-integrated-as ; PR11125 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" target triple = "x86_64-apple-macosx10.7" diff --git a/llvm/test/CodeGen/X86/asm-block-labels.ll b/llvm/test/CodeGen/X86/asm-block-labels.ll index a43d4302319..6dbfb16a6d5 100644 --- a/llvm/test/CodeGen/X86/asm-block-labels.ll +++ b/llvm/test/CodeGen/X86/asm-block-labels.ll @@ -1,4 +1,4 @@ -; RUN: opt < %s -std-compile-opts | llc +; RUN: opt < %s -std-compile-opts | llc -no-integrated-as ; ModuleID = 'block12.c' target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" target triple = "i686-apple-darwin8" diff --git a/llvm/test/CodeGen/X86/asm-global-imm.ll b/llvm/test/CodeGen/X86/asm-global-imm.ll index ebf585a39a2..9e79f6f7822 100644 --- a/llvm/test/CodeGen/X86/asm-global-imm.ll +++ b/llvm/test/CodeGen/X86/asm-global-imm.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 -relocation-model=static | FileCheck %s +; RUN: llc < %s -march=x86 -relocation-model=static -no-integrated-as | FileCheck %s ; PR882 target datalayout = "e-p:32:32" diff --git a/llvm/test/CodeGen/X86/cas.ll b/llvm/test/CodeGen/X86/cas.ll index c2dd05ef730..ec519c646f6 100644 --- a/llvm/test/CodeGen/X86/cas.ll +++ b/llvm/test/CodeGen/X86/cas.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=x86_64-pc-linux-gnu %s -o - | FileCheck %s +; RUN: llc -mtriple=x86_64-pc-linux-gnu %s -o - -no-integrated-as | FileCheck %s ; C code this came from ;bool cas(float volatile *p, float *expected, float desired) { diff --git a/llvm/test/CodeGen/X86/crash.ll b/llvm/test/CodeGen/X86/crash.ll index 051150e227a..ee73377dffd 100644 --- a/llvm/test/CodeGen/X86/crash.ll +++ b/llvm/test/CodeGen/X86/crash.ll @@ -1,7 +1,7 @@ ; REQUIRES: asserts -; RUN: llc -march=x86 < %s -verify-machineinstrs -precompute-phys-liveness -; RUN: llc -march=x86-64 < %s -verify-machineinstrs -precompute-phys-liveness - +; RUN: llc -march=x86 -no-integrated-as < %s -verify-machineinstrs -precompute-phys-liveness +; RUN: llc -march=x86-64 -no-integrated-as < %s -verify-machineinstrs -precompute-phys-liveness + ; PR6497 ; Chain and flag folding issues. diff --git a/llvm/test/CodeGen/X86/fast-isel.ll b/llvm/test/CodeGen/X86/fast-isel.ll index 132df2b0ab4..bc791842160 100644 --- a/llvm/test/CodeGen/X86/fast-isel.ll +++ b/llvm/test/CodeGen/X86/fast-isel.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -fast-isel -fast-isel-abort -verify-machineinstrs -march=x86 -mattr=sse2 -; RUN: llc < %s -fast-isel -fast-isel-abort -verify-machineinstrs -mtriple=x86_64-apple-darwin10 +; RUN: llc < %s -fast-isel -fast-isel-abort -verify-machineinstrs -march=x86 -mattr=sse2 -no-integrated-as +; RUN: llc < %s -fast-isel -fast-isel-abort -verify-machineinstrs -mtriple=x86_64-apple-darwin10 -no-integrated-as ; This tests very minimal fast-isel functionality. diff --git a/llvm/test/CodeGen/X86/fold-xmm-zero.ll b/llvm/test/CodeGen/X86/fold-xmm-zero.ll index b4eeb409838..c92d45c35ae 100644 --- a/llvm/test/CodeGen/X86/fold-xmm-zero.ll +++ b/llvm/test/CodeGen/X86/fold-xmm-zero.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=i386-apple-macosx10.6.7 -mattr=+sse2 | FileCheck %s +; RUN: llc < %s -mtriple=i386-apple-macosx10.6.7 -mattr=+sse2 -no-integrated-as | FileCheck %s ; Simple test to make sure folding for special constants (like float zero) ; isn't completely broken. diff --git a/llvm/test/CodeGen/X86/inline-asm-flag-clobber.ll b/llvm/test/CodeGen/X86/inline-asm-flag-clobber.ll index 45f4d2f38a4..bb7c33e422e 100644 --- a/llvm/test/CodeGen/X86/inline-asm-flag-clobber.ll +++ b/llvm/test/CodeGen/X86/inline-asm-flag-clobber.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=x86-64 < %s | FileCheck %s +; RUN: llc -march=x86-64 -no-integrated-as < %s | FileCheck %s ; PR3701 define i64 @t(i64* %arg) nounwind { diff --git a/llvm/test/CodeGen/X86/inline-asm-fpstack.ll b/llvm/test/CodeGen/X86/inline-asm-fpstack.ll index e83c065632d..91c477baaa5 100644 --- a/llvm/test/CodeGen/X86/inline-asm-fpstack.ll +++ b/llvm/test/CodeGen/X86/inline-asm-fpstack.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mcpu=generic -mtriple=i386-apple-darwin | FileCheck %s +; RUN: llc < %s -mcpu=generic -mtriple=i386-apple-darwin -no-integrated-as | FileCheck %s ; There should be no stack manipulations between the inline asm and ret. ; CHECK: test1 diff --git a/llvm/test/CodeGen/X86/inline-asm-h.ll b/llvm/test/CodeGen/X86/inline-asm-h.ll index 53cf419bd11..8c3e45aba90 100644 --- a/llvm/test/CodeGen/X86/inline-asm-h.ll +++ b/llvm/test/CodeGen/X86/inline-asm-h.ll @@ -9,4 +9,4 @@ entry: } ; CHECK: zed -; CHECK: movq %mm2,foobar+8(%rip) +; CHECK: movq %mm2, foobar+8(%rip) diff --git a/llvm/test/CodeGen/X86/inline-asm-modifier-n.ll b/llvm/test/CodeGen/X86/inline-asm-modifier-n.ll index b069c463189..072c7c41953 100644 --- a/llvm/test/CodeGen/X86/inline-asm-modifier-n.ll +++ b/llvm/test/CodeGen/X86/inline-asm-modifier-n.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 | grep " 37" +; RUN: llc < %s -march=x86 -no-integrated-as | grep " 37" ; rdar://7008959 define void @bork() nounwind { diff --git a/llvm/test/CodeGen/X86/inline-asm-mrv.ll b/llvm/test/CodeGen/X86/inline-asm-mrv.ll index 733205d6a91..a96e7b81807 100644 --- a/llvm/test/CodeGen/X86/inline-asm-mrv.ll +++ b/llvm/test/CodeGen/X86/inline-asm-mrv.ll @@ -1,8 +1,8 @@ ; PR2094 -; RUN: llc < %s -march=x86-64 | grep movslq -; RUN: llc < %s -march=x86-64 | grep addps -; RUN: llc < %s -march=x86-64 | grep paddd -; RUN: llc < %s -march=x86-64 | not grep movq +; RUN: llc < %s -march=x86-64 -no-integrated-as | grep movslq +; RUN: llc < %s -march=x86-64 -no-integrated-as | grep addps +; RUN: llc < %s -march=x86-64 -no-integrated-as | grep paddd +; RUN: llc < %s -march=x86-64 -no-integrated-as | not grep movq target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" target triple = "x86_64-apple-darwin8" diff --git a/llvm/test/CodeGen/X86/inline-asm-q-regs.ll b/llvm/test/CodeGen/X86/inline-asm-q-regs.ll index fca68baac6e..53a56aee2cb 100644 --- a/llvm/test/CodeGen/X86/inline-asm-q-regs.ll +++ b/llvm/test/CodeGen/X86/inline-asm-q-regs.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86-64 -mattr=+avx +; RUN: llc < %s -march=x86-64 -mattr=+avx -no-integrated-as ; rdar://7066579 %0 = type { i64, i64, i64, i64, i64 } ; type %0 diff --git a/llvm/test/CodeGen/X86/inline-asm-stack-realign3.ll b/llvm/test/CodeGen/X86/inline-asm-stack-realign3.ll index cdb77ca3ea3..3baaaaa7d93 100644 --- a/llvm/test/CodeGen/X86/inline-asm-stack-realign3.ll +++ b/llvm/test/CodeGen/X86/inline-asm-stack-realign3.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=x86 < %s | FileCheck %s +; RUN: llc -march=x86 -no-integrated-as < %s | FileCheck %s declare void @bar(i32* %junk) diff --git a/llvm/test/CodeGen/X86/inline-asm-tied.ll b/llvm/test/CodeGen/X86/inline-asm-tied.ll index 597236e3628..fb5896b0ad6 100644 --- a/llvm/test/CodeGen/X86/inline-asm-tied.ll +++ b/llvm/test/CodeGen/X86/inline-asm-tied.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=i386-apple-darwin9 -O0 -optimize-regalloc -regalloc=basic | FileCheck %s +; RUN: llc < %s -mtriple=i386-apple-darwin9 -O0 -optimize-regalloc -regalloc=basic -no-integrated-as | FileCheck %s ; rdar://6992609 ; CHECK: movl [[EDX:%e..]], 4(%esp) diff --git a/llvm/test/CodeGen/X86/inline-asm-x-scalar.ll b/llvm/test/CodeGen/X86/inline-asm-x-scalar.ll index 5a9628b3df7..64a7fe82647 100644 --- a/llvm/test/CodeGen/X86/inline-asm-x-scalar.ll +++ b/llvm/test/CodeGen/X86/inline-asm-x-scalar.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 -mcpu=yonah +; RUN: llc < %s -march=x86 -mcpu=yonah -no-integrated-as define void @test1() { tail call void asm sideeffect "ucomiss $0", "x"( float 0x41E0000000000000) diff --git a/llvm/test/CodeGen/X86/inline-asm.ll b/llvm/test/CodeGen/X86/inline-asm.ll index f12c2600fff..5ec4f469df8 100644 --- a/llvm/test/CodeGen/X86/inline-asm.ll +++ b/llvm/test/CodeGen/X86/inline-asm.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 +; RUN: llc < %s -march=x86 -no-integrated-as define i32 @test1() nounwind { ; Dest is AX, dest type = i32. diff --git a/llvm/test/CodeGen/X86/mature-mc-support.ll b/llvm/test/CodeGen/X86/mature-mc-support.ll new file mode 100644 index 00000000000..9d956f46bec --- /dev/null +++ b/llvm/test/CodeGen/X86/mature-mc-support.ll @@ -0,0 +1,18 @@ +; Test that inline assembly is parsed by the MC layer when MC support is mature +; (even when the output is assembly). + +; RUN: not llc -march=x86 < %s > /dev/null 2> %t1 +; RUN: FileCheck %s < %t1 + +; RUN: not llc -march=x86 -filetype=obj < %s > /dev/null 2> %t2 +; RUN: FileCheck %s < %t2 + +; RUN: not llc -march=x86-64 < %s > /dev/null 2> %t3 +; RUN: FileCheck %s < %t3 + +; RUN: not llc -march=x86-64 -filetype=obj < %s > /dev/null 2> %t4 +; RUN: FileCheck %s < %t4 + +module asm " .this_directive_is_very_unlikely_to_exist" + +; CHECK: LLVM ERROR: Error parsing inline asm diff --git a/llvm/test/CodeGen/X86/ms-inline-asm.ll b/llvm/test/CodeGen/X86/ms-inline-asm.ll index 436d34a1155..69105158906 100644 --- a/llvm/test/CodeGen/X86/ms-inline-asm.ll +++ b/llvm/test/CodeGen/X86/ms-inline-asm.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 -mcpu=core2 | FileCheck %s +; RUN: llc < %s -march=x86 -mcpu=core2 -no-integrated-as | FileCheck %s define i32 @t1() nounwind { entry: diff --git a/llvm/test/CodeGen/X86/mult-alt-generic-i686.ll b/llvm/test/CodeGen/X86/mult-alt-generic-i686.ll index 7c3499f178a..54bc3a42f03 100644 --- a/llvm/test/CodeGen/X86/mult-alt-generic-i686.ll +++ b/llvm/test/CodeGen/X86/mult-alt-generic-i686.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 +; RUN: llc < %s -march=x86 -no-integrated-as ; ModuleID = 'mult-alt-generic.c' target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32-n8:16:32" target triple = "i686" diff --git a/llvm/test/CodeGen/X86/mult-alt-generic-x86_64.ll b/llvm/test/CodeGen/X86/mult-alt-generic-x86_64.ll index f35bb5e3407..84a9c814094 100644 --- a/llvm/test/CodeGen/X86/mult-alt-generic-x86_64.ll +++ b/llvm/test/CodeGen/X86/mult-alt-generic-x86_64.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86-64 +; RUN: llc < %s -march=x86-64 -no-integrated-as ; ModuleID = 'mult-alt-generic.c' target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" target triple = "x86_64" diff --git a/llvm/test/CodeGen/X86/mult-alt-x86.ll b/llvm/test/CodeGen/X86/mult-alt-x86.ll index 06175da4645..cb2219a6ed7 100644 --- a/llvm/test/CodeGen/X86/mult-alt-x86.ll +++ b/llvm/test/CodeGen/X86/mult-alt-x86.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 -mattr=+sse2 +; RUN: llc < %s -march=x86 -mattr=+sse2 -no-integrated-as ; ModuleID = 'mult-alt-x86.c' target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f80:128:128-v64:64:64-v128:128:128-a0:0:64-f80:32:32-n8:16:32" target triple = "i686-pc-win32" diff --git a/llvm/test/CodeGen/X86/multiple-loop-post-inc.ll b/llvm/test/CodeGen/X86/multiple-loop-post-inc.ll index 29b9f34464f..4edc1ff0b3f 100644 --- a/llvm/test/CodeGen/X86/multiple-loop-post-inc.ll +++ b/llvm/test/CodeGen/X86/multiple-loop-post-inc.ll @@ -1,4 +1,4 @@ -; RUN: llc -asm-verbose=false -disable-branch-fold -disable-block-placement -disable-tail-duplicate -march=x86-64 -mcpu=nehalem < %s | FileCheck %s +; RUN: llc -asm-verbose=false -disable-branch-fold -disable-block-placement -disable-tail-duplicate -march=x86-64 -mcpu=nehalem -no-integrated-as < %s | FileCheck %s ; rdar://7236213 ; ; The scheduler's 2-address hack has been disabled, so there is diff --git a/llvm/test/CodeGen/X86/opaque-constant-asm.ll b/llvm/test/CodeGen/X86/opaque-constant-asm.ll index ab3d4e8b168..dd1cc8ec483 100644 --- a/llvm/test/CodeGen/X86/opaque-constant-asm.ll +++ b/llvm/test/CodeGen/X86/opaque-constant-asm.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-apple-darwin -no-integrated-as | FileCheck %s ; This tests makes sure that we not mistake the bitcast inside the asm statement ; as an opaque constant. If we do, then the compilation will simply fail. diff --git a/llvm/test/Transforms/BranchFolding/2007-10-19-InlineAsmDirectives.ll b/llvm/test/Transforms/BranchFolding/2007-10-19-InlineAsmDirectives.ll index 9d82819f9db..598ea0e354e 100644 --- a/llvm/test/Transforms/BranchFolding/2007-10-19-InlineAsmDirectives.ll +++ b/llvm/test/Transforms/BranchFolding/2007-10-19-InlineAsmDirectives.ll @@ -1,4 +1,4 @@ -; RUN: opt < %s -std-compile-opts -o - | llc -o - | grep bork_directive | wc -l | grep 2 +; RUN: opt < %s -std-compile-opts -o - | llc -no-integrated-as -o - | grep bork_directive | wc -l | grep 2 ;; We don't want branch folding to fold asm directives. |
