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-rw-r--r--llvm/lib/Target/AArch64/AArch64CallingConvention.h5
-rw-r--r--llvm/test/CodeGen/AArch64/argument-blocks.ll7
2 files changed, 12 insertions, 0 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64CallingConvention.h b/llvm/lib/Target/AArch64/AArch64CallingConvention.h
index 8c798b71bec..baf80bc5483 100644
--- a/llvm/lib/Target/AArch64/AArch64CallingConvention.h
+++ b/llvm/lib/Target/AArch64/AArch64CallingConvention.h
@@ -28,6 +28,9 @@ using namespace llvm;
static const uint16_t XRegList[] = {AArch64::X0, AArch64::X1, AArch64::X2,
AArch64::X3, AArch64::X4, AArch64::X5,
AArch64::X6, AArch64::X7};
+static const uint16_t HRegList[] = {AArch64::H0, AArch64::H1, AArch64::H2,
+ AArch64::H3, AArch64::H4, AArch64::H5,
+ AArch64::H6, AArch64::H7};
static const uint16_t SRegList[] = {AArch64::S0, AArch64::S1, AArch64::S2,
AArch64::S3, AArch64::S4, AArch64::S5,
AArch64::S6, AArch64::S7};
@@ -88,6 +91,8 @@ static bool CC_AArch64_Custom_Block(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
ArrayRef<uint16_t> RegList;
if (LocVT.SimpleTy == MVT::i64)
RegList = XRegList;
+ else if (LocVT.SimpleTy == MVT::f16)
+ RegList = HRegList;
else if (LocVT.SimpleTy == MVT::f32 || LocVT.is32BitVector())
RegList = SRegList;
else if (LocVT.SimpleTy == MVT::f64 || LocVT.is64BitVector())
diff --git a/llvm/test/CodeGen/AArch64/argument-blocks.ll b/llvm/test/CodeGen/AArch64/argument-blocks.ll
index 9204da8d7eb..f1dcfa67d0e 100644
--- a/llvm/test/CodeGen/AArch64/argument-blocks.ll
+++ b/llvm/test/CodeGen/AArch64/argument-blocks.ll
@@ -188,3 +188,10 @@ define <16 x i8> @test_v16i8_blocked([7 x double], [2 x <16 x i8>] %in) {
%val = extractvalue [2 x <16 x i8>] %in, 0
ret <16 x i8> %val
}
+
+define half @test_f16_blocked([7 x double], [2 x half] %in) {
+; CHECK-LABEL: test_f16_blocked:
+; CHECK: ldr h0, [sp]
+ %val = extractvalue [2 x half] %in, 0
+ ret half %val
+}
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