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-rw-r--r--llvm/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h17
1 files changed, 17 insertions, 0 deletions
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h b/llvm/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h
index 6469806dc9e..f78df0703af 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h
@@ -195,6 +195,23 @@ public:
/// Get the total number of register banks.
unsigned getNumRegBanks() const { return NumRegBanks; }
+ /// Get a register bank that covers \p RC.
+ ///
+ /// \pre \p RC is a user-defined register class (as opposed as one
+ /// generated by TableGen).
+ ///
+ /// \note The mapping RC -> RegBank could be built while adding the
+ /// coverage for the register banks. However, we do not do it, because,
+ /// at least for now, we only need this information for register classes
+ /// that are used in the description of instruction. In other words,
+ /// there are just a handful of them and we do not want to waste space.
+ ///
+ /// \todo This should be TableGen'ed.
+ virtual const RegisterBank &
+ getRegBankFromRegClass(const TargetRegisterClass &RC) const {
+ llvm_unreachable("The target must override this method");
+ }
+
/// Get the cost of a copy from \p B to \p A, or put differently,
/// get the cost of A = COPY B.
virtual unsigned copyCost(const RegisterBank &A,
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