diff options
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp | 7 | ||||
| -rw-r--r-- | llvm/test/Transforms/InstCombine/atomic.ll | 34 |
2 files changed, 37 insertions, 4 deletions
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp b/llvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp index aa72244463e..e8314006dd1 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp @@ -1193,10 +1193,6 @@ Instruction *InstCombiner::visitStoreInst(StoreInst &SI) { if (isa<UndefValue>(Val)) return eraseInstFromFunction(SI); - // The code below needs to be audited and adjusted for unordered atomics - if (!SI.isSimple()) - return nullptr; - // If this store is the last instruction in the basic block (possibly // excepting debug info instructions), and if the block ends with an // unconditional branch, try to move it to the successor block. @@ -1222,6 +1218,9 @@ Instruction *InstCombiner::visitStoreInst(StoreInst &SI) { /// into a phi node with a store in the successor. /// bool InstCombiner::SimplifyStoreAtEndOfBlock(StoreInst &SI) { + assert(SI.isUnordered() && + "this code has not been auditted for volatile or ordered store case"); + BasicBlock *StoreBB = SI.getParent(); // Check to see if the successor block has exactly two incoming edges. If diff --git a/llvm/test/Transforms/InstCombine/atomic.ll b/llvm/test/Transforms/InstCombine/atomic.ll index 408bc8166e9..b1c4a2967fa 100644 --- a/llvm/test/Transforms/InstCombine/atomic.ll +++ b/llvm/test/Transforms/InstCombine/atomic.ll @@ -211,3 +211,37 @@ define i32 @test21(i32** %p, i8* %v) { store atomic i32* %cast, i32** %p monotonic, align 4 ret i32 0 } + +define i32 @test22(i1 %cnd) { +; CHECK-LABEL: define i32 @test22( +; CHECK: [[PHI:%.*]] = phi i32 +; CHECK: store atomic i32 [[PHI]], i32* @a unordered, align 4 + br i1 %cnd, label %block1, label %block2 + +block1: + store atomic i32 1, i32* @a unordered, align 4 + br label %merge +block2: + store atomic i32 2, i32* @a unordered, align 4 + br label %merge + +merge: + ret i32 0 +} + +; TODO: probably also legal here +define i32 @test23(i1 %cnd) { +; CHECK-LABEL: define i32 @test23( +; CHECK: br i1 %cnd, label %block1, label %block2 + br i1 %cnd, label %block1, label %block2 + +block1: + store atomic i32 1, i32* @a monotonic, align 4 + br label %merge +block2: + store atomic i32 2, i32* @a monotonic, align 4 + br label %merge + +merge: + ret i32 0 +} |
