diff options
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCInstrInfo.cpp | 19 | ||||
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir | 4 |
2 files changed, 14 insertions, 9 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp index d26af451303..1b9d5d2d8e0 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp @@ -3438,15 +3438,20 @@ bool PPCInstrInfo::transformToImmFormFedByLI(MachineInstr &MI, if (III.OpNoForForwarding != III.ImmOpNo) swapMIOperands(MI, III.OpNoForForwarding, III.ImmOpNo); - // If the R0/X0 register is special for the original instruction and not for - // the new instruction (or vice versa), we need to fix up the register class. + // If the special R0/X0 register index are different for original instruction + // and new instruction, we need to fix up the register class in new + // instruction. if (!PostRA && III.ZeroIsSpecialOrig != III.ZeroIsSpecialNew) { - if (!III.ZeroIsSpecialOrig) { + if (III.ZeroIsSpecialNew) { + // If operand at III.ZeroIsSpecialNew is physical reg(eg: ZERO/ZERO8), no + // need to fix up register class. unsigned RegToModify = MI.getOperand(III.ZeroIsSpecialNew).getReg(); - const TargetRegisterClass *NewRC = - MRI.getRegClass(RegToModify)->hasSuperClassEq(&PPC::GPRCRegClass) ? - &PPC::GPRC_and_GPRC_NOR0RegClass : &PPC::G8RC_and_G8RC_NOX0RegClass; - MRI.setRegClass(RegToModify, NewRC); + if (TargetRegisterInfo::isVirtualRegister(RegToModify)) { + const TargetRegisterClass *NewRC = + MRI.getRegClass(RegToModify)->hasSuperClassEq(&PPC::GPRCRegClass) ? + &PPC::GPRC_and_GPRC_NOR0RegClass : &PPC::G8RC_and_G8RC_NOX0RegClass; + MRI.setRegClass(RegToModify, NewRC); + } } } return true; diff --git a/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir b/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir index e210ec5c523..eb058bc9b7d 100644 --- a/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir +++ b/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir @@ -1,5 +1,5 @@ -# RUN: llc -run-pass ppc-mi-peepholes -ppc-convert-rr-to-ri %s -o - | FileCheck %s -# RUN: llc -start-after ppc-mi-peepholes -ppc-late-peephole %s -o - | FileCheck %s --check-prefix=CHECK-LATE +# RUN: llc -run-pass ppc-mi-peepholes -ppc-convert-rr-to-ri %s -o - -verify-machineinstrs | FileCheck %s +# RUN: llc -start-after ppc-mi-peepholes -ppc-late-peephole %s -o - -verify-machineinstrs | FileCheck %s --check-prefix=CHECK-LATE --- | ; ModuleID = 'convert-rr-to-ri-instrs.ll' |
