diff options
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/lib/Target/ARM64/ARM64InstrFormats.td | 12 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM64/ARM64InstrInfo.td | 32 |
2 files changed, 21 insertions, 23 deletions
diff --git a/llvm/lib/Target/ARM64/ARM64InstrFormats.td b/llvm/lib/Target/ARM64/ARM64InstrFormats.td index 8133a0084f7..11d2e4312c7 100644 --- a/llvm/lib/Target/ARM64/ARM64InstrFormats.td +++ b/llvm/lib/Target/ARM64/ARM64InstrFormats.td @@ -1606,12 +1606,6 @@ multiclass AddSub<bit isSub, string mnemonic, let Inst{31} = 1; } - // Register/register aliases with no shift when SP is not used. - def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Wrs"), - GPR32, GPR32, GPR32, 0>; - def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Xrs"), - GPR64, GPR64, GPR64, 0>; - // Register/register aliases with no shift when either the destination or // first source register is SP. This relies on the shifted register aliases // above matching first in the case when SP is not used. @@ -1690,12 +1684,6 @@ multiclass AddSubS<bit isSub, string mnemonic, SDNode OpNode, string cmp> { def : InstAlias<cmp#" $src1, $src2", (!cast<Instruction>(NAME#"Xrs") XZR, GPR64:$src1, GPR64:$src2, 0)>; - // Register/register aliases with no shift when SP is not used. - def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Wrs"), - GPR32, GPR32, GPR32, 0>; - def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Xrs"), - GPR64, GPR64, GPR64, 0>; - // Register/register aliases with no shift when the first source register // is SP. This relies on the shifted register aliases above matching first // in the case when SP is not used. diff --git a/llvm/lib/Target/ARM64/ARM64InstrInfo.td b/llvm/lib/Target/ARM64/ARM64InstrInfo.td index 5d46ac6125a..bf868834548 100644 --- a/llvm/lib/Target/ARM64/ARM64InstrInfo.td +++ b/llvm/lib/Target/ARM64/ARM64InstrInfo.td @@ -554,15 +554,6 @@ def : Pat<(sub GPR64:$Rn, neg_addsub_shifted_imm64:$imm), (ADDXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>; } -// FIXME: TableGen can very nearly handle printing all of these, we should make -// it work properly. -def : InstAlias<"neg $dst, $src", (SUBWrs GPR32:$dst, WZR, GPR32:$src, 0)>; -def : InstAlias<"neg $dst, $src", (SUBXrs GPR64:$dst, XZR, GPR64:$src, 0)>; -def : InstAlias<"neg $dst, $src, $shift", - (SUBWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift)>; -def : InstAlias<"neg $dst, $src, $shift", - (SUBXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift)>; - // Because of the immediate format for add/sub-imm instructions, the // expression (add x, -1) must be transformed to (SUB{W,X}ri x, 1). // These patterns capture that transformation. @@ -577,13 +568,32 @@ def : Pat<(ARM64sub_flag GPR64:$Rn, neg_addsub_shifted_imm64:$imm), (ADDSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>; } +def : InstAlias<"neg $dst, $src", (SUBWrs GPR32:$dst, WZR, GPR32:$src, 0)>; +def : InstAlias<"neg $dst, $src", (SUBXrs GPR64:$dst, XZR, GPR64:$src, 0)>; +def : InstAlias<"neg $dst, $src$shift", + (SUBWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift)>; +def : InstAlias<"neg $dst, $src$shift", + (SUBXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift)>; + def : InstAlias<"negs $dst, $src", (SUBSWrs GPR32:$dst, WZR, GPR32:$src, 0)>; def : InstAlias<"negs $dst, $src", (SUBSXrs GPR64:$dst, XZR, GPR64:$src, 0)>; -def : InstAlias<"negs $dst, $src, $shift", +def : InstAlias<"negs $dst, $src$shift", (SUBSWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift)>; -def : InstAlias<"negs $dst, $src, $shift", +def : InstAlias<"negs $dst, $src$shift", (SUBSXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift)>; + +// Register/register aliases with no shift when SP is not used. +def : AddSubRegAlias<"add", ADDWrs, GPR32, GPR32, GPR32, 0>; +def : AddSubRegAlias<"add", ADDXrs, GPR64, GPR64, GPR64, 0>; +def : AddSubRegAlias<"sub", SUBWrs, GPR32, GPR32, GPR32, 0>; +def : AddSubRegAlias<"sub", SUBXrs, GPR64, GPR64, GPR64, 0>; +def : AddSubRegAlias<"adds", ADDSWrs, GPR32, GPR32, GPR32, 0>; +def : AddSubRegAlias<"adds", ADDSXrs, GPR64, GPR64, GPR64, 0>; +def : AddSubRegAlias<"subs", SUBSWrs, GPR32, GPR32, GPR32, 0>; +def : AddSubRegAlias<"subs", SUBSXrs, GPR64, GPR64, GPR64, 0>; + + // Unsigned/Signed divide defm UDIV : Div<0, "udiv", udiv>; defm SDIV : Div<1, "sdiv", sdiv>; |
