diff options
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVInstrInfoF.td | 22 | ||||
| -rw-r--r-- | llvm/test/MC/RISCV/rv32f-invalid.s | 2 | ||||
| -rw-r--r-- | llvm/test/MC/RISCV/rv64f-invalid.s | 9 | ||||
| -rw-r--r-- | llvm/test/MC/RISCV/rv64f-valid.s | 37 |
4 files changed, 70 insertions, 0 deletions
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoF.td b/llvm/lib/Target/RISCV/RISCVInstrInfoF.td index ea2d4175e79..a95d093e7c7 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoF.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoF.td @@ -165,3 +165,25 @@ def FMV_W_X : FPUnaryOp_r<0b1111000, 0b000, FPR32, GPR, "fmv.w.x"> { let rs2 = 0b00000; } } // Predicates = [HasStdExtF] + +let Predicates = [HasStdExtF, IsRV64] in { +def FCVT_L_S : FPUnaryOp_r_frm<0b1100000, GPR, FPR32, "fcvt.l.s"> { + let rs2 = 0b00010; +} +def : FPUnaryOpDynFrmAlias<FCVT_L_S, "fcvt.l.s", GPR, FPR32>; + +def FCVT_LU_S : FPUnaryOp_r_frm<0b1100000, GPR, FPR32, "fcvt.lu.s"> { + let rs2 = 0b00011; +} +def : FPUnaryOpDynFrmAlias<FCVT_LU_S, "fcvt.lu.s", GPR, FPR32>; + +def FCVT_S_L : FPUnaryOp_r_frm<0b1101000, FPR32, GPR, "fcvt.s.l"> { + let rs2 = 0b00010; +} +def : FPUnaryOpDynFrmAlias<FCVT_S_L, "fcvt.s.l", FPR32, GPR>; + +def FCVT_S_LU : FPUnaryOp_r_frm<0b1101000, FPR32, GPR, "fcvt.s.lu"> { + let rs2 = 0b00011; +} +def : FPUnaryOpDynFrmAlias<FCVT_S_LU, "fcvt.s.lu", FPR32, GPR>; +} // Predicates = [HasStdExtF, IsRV64] diff --git a/llvm/test/MC/RISCV/rv32f-invalid.s b/llvm/test/MC/RISCV/rv32f-invalid.s index f22fa7ac5dd..ed9aaed1bca 100644 --- a/llvm/test/MC/RISCV/rv32f-invalid.s +++ b/llvm/test/MC/RISCV/rv32f-invalid.s @@ -30,3 +30,5 @@ fnmsub.s f18, f19, f20, f21, 0b111 # CHECK: :[[@LINE]]:30: error: operand must b # Using 'D' instructions for an 'F'-only target fadd.d ft0, ft1, ft2 # CHECK: :[[@LINE]]:1: error: instruction use requires an option to be enabled + +# Using RV64F instructions for RV32 is tested in rv64f-valid.s diff --git a/llvm/test/MC/RISCV/rv64f-invalid.s b/llvm/test/MC/RISCV/rv64f-invalid.s new file mode 100644 index 00000000000..698da796a7e --- /dev/null +++ b/llvm/test/MC/RISCV/rv64f-invalid.s @@ -0,0 +1,9 @@ +# RUN: not llvm-mc -triple riscv64 -mattr=+f < %s 2>&1 | FileCheck %s + +# Integer registers where FP regs are expected +fcvt.l.s ft0, a0 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction +fcvt.lu.s ft1, a1 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction + +# FP registers where integer regs are expected +fcvt.s.l a2, ft2 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction +fcvt.s.lu a3, ft3 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction diff --git a/llvm/test/MC/RISCV/rv64f-valid.s b/llvm/test/MC/RISCV/rv64f-valid.s new file mode 100644 index 00000000000..eda826dfd97 --- /dev/null +++ b/llvm/test/MC/RISCV/rv64f-valid.s @@ -0,0 +1,37 @@ +# RUN: llvm-mc %s -triple=riscv64 -mattr=+f -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s +# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+f < %s \ +# RUN: | llvm-objdump -mattr=+f -d - | FileCheck -check-prefix=CHECK-INST %s +# RUN: not llvm-mc -triple riscv32 -mattr=+f < %s 2>&1 \ +# RUN: | FileCheck -check-prefix=CHECK-RV32 %s + +# CHECK-INST: fcvt.l.s a0, ft0 +# CHECK: encoding: [0x53,0x75,0x20,0xc0] +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled +fcvt.l.s a0, ft0 +# CHECK-INST: fcvt.lu.s a1, ft1 +# CHECK: encoding: [0xd3,0xf5,0x30,0xc0] +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled +fcvt.lu.s a1, ft1 +# CHECK-INST: fcvt.s.l ft2, a2 +# CHECK: encoding: [0x53,0x71,0x26,0xd0] +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled +fcvt.s.l ft2, a2 +# CHECK-INST: fcvt.s.lu ft3, a3 +# CHECK: encoding: [0xd3,0xf1,0x36,0xd0] +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled +fcvt.s.lu ft3, a3 + +# Rounding modes +# CHECK-INST: fcvt.l.s a4, ft4, rne +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled +fcvt.l.s a4, ft4, rne +# CHECK-INST: fcvt.lu.s a5, ft5, rtz +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled +fcvt.lu.s a5, ft5, rtz +# CHECK-INST: fcvt.s.l ft6, a6, rdn +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled +fcvt.s.l ft6, a6, rdn +# CHECK-INST: fcvt.s.lu ft7, a7, rup +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled +fcvt.s.lu ft7, a7, rup |
