diff options
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp | 12 | ||||
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 14 | ||||
| -rw-r--r-- | llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.cpp | 11 | ||||
| -rw-r--r-- | llvm/test/CodeGen/RISCV/subtarget-features-std-ext.ll | 11 |
4 files changed, 13 insertions, 35 deletions
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp index 53562f42a18..cfd83e4189f 100644 --- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp +++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp @@ -194,18 +194,6 @@ public: Parser.addAliasForDirective(".word", ".4byte"); Parser.addAliasForDirective(".dword", ".8byte"); setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); - - if (Options.ABIName.back() == 'f' && - !getSTI().getFeatureBits()[RISCV::FeatureStdExtF]) { - errs() << "Hard-float 'f' ABI can't be used for a target that " - "doesn't support the F instruction set extension (ignoring " - "target-abi)\n"; - } else if (Options.ABIName.back() == 'd' && - !getSTI().getFeatureBits()[RISCV::FeatureStdExtD]) { - errs() << "Hard-float 'd' ABI can't be used for a target that " - "doesn't support the D instruction set extension (ignoring " - "target-abi)\n"; - } } }; diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 5a2cffbc824..0b1fd382366 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -51,20 +51,6 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM, RISCVABI::ABI ABI = Subtarget.getTargetABI(); assert(ABI != RISCVABI::ABI_Unknown && "Improperly initialised target ABI"); - if ((ABI == RISCVABI::ABI_ILP32F || ABI == RISCVABI::ABI_LP64F) && - !Subtarget.hasStdExtF()) { - errs() << "Hard-float 'f' ABI can't be used for a target that " - "doesn't support the F instruction set extension (ignoring " - "target-abi)\n"; - ABI = Subtarget.is64Bit() ? RISCVABI::ABI_LP64 : RISCVABI::ABI_ILP32; - } else if ((ABI == RISCVABI::ABI_ILP32D || ABI == RISCVABI::ABI_LP64D) && - !Subtarget.hasStdExtD()) { - errs() << "Hard-float 'd' ABI can't be used for a target that " - "doesn't support the D instruction set extension (ignoring " - "target-abi)\n"; - ABI = Subtarget.is64Bit() ? RISCVABI::ABI_LP64 : RISCVABI::ABI_ILP32; - } - switch (ABI) { default: report_fatal_error("Don't know how to lower this ABI"); diff --git a/llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.cpp b/llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.cpp index 43b1f8b80c5..da87722632e 100644 --- a/llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.cpp +++ b/llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.cpp @@ -28,8 +28,17 @@ ABI computeTargetABI(const Triple &TT, FeatureBitset FeatureBits, errs() << "64-bit ABIs are not supported for 32-bit targets (ignoring " "target-abi)\n"; TargetABI = ABI_Unknown; + } else if (ABIName.endswith("f") && !FeatureBits[RISCV::FeatureStdExtF]) { + errs() << "Hard-float 'f' ABI can't be used for a target that " + "doesn't support the F instruction set extension (ignoring " + "target-abi)\n"; + TargetABI = ABI_Unknown; + } else if (ABIName.endswith("d") && !FeatureBits[RISCV::FeatureStdExtD]) { + errs() << "Hard-float 'd' ABI can't be used for a target that " + "doesn't support the D instruction set extension (ignoring " + "target-abi)\n"; + TargetABI = ABI_Unknown; } else if (IsRV32E && TargetABI != ABI_ILP32E && TargetABI != ABI_Unknown) { - // TODO: move this checking to RISCVTargetLowering and RISCVAsmParser errs() << "Only the ilp32e ABI is supported for RV32E (ignoring target-abi)\n"; TargetABI = ABI_Unknown; diff --git a/llvm/test/CodeGen/RISCV/subtarget-features-std-ext.ll b/llvm/test/CodeGen/RISCV/subtarget-features-std-ext.ll index 613a983f926..8ed465ae85f 100644 --- a/llvm/test/CodeGen/RISCV/subtarget-features-std-ext.ll +++ b/llvm/test/CodeGen/RISCV/subtarget-features-std-ext.ll @@ -2,17 +2,12 @@ ; RUN: | FileCheck -check-prefix=RV32IF-ILP32 %s ; RUN: llc -mtriple=riscv32 -target-abi ilp32f < %s 2>&1 \ ; RUN: | FileCheck -check-prefix=RV32IF-ILP32F %s -; RUN: llc -mtriple=riscv32 -mattr=-f -target-abi ilp32f <%s 2>&1 \ -; RUN: | FileCheck -check-prefix=RV32I-ILP32F-FAILED %s - -; RV32I-ILP32F-FAILED: Hard-float 'f' ABI can't be used for a target that doesn't support the F instruction set extension +; RV32IF-ILP32F: Hard-float 'f' ABI can't be used for a target that doesn't support the F instruction set extension (ignoring target-abi) define float @foo(i32 %a) nounwind #0 { -; RV32IF-ILP32: fcvt.s.w ft0, a0 -; RV32IF-ILP32-NEXT: fmv.x.w a0, ft0 -; RV32IF-ILP32F: fcvt.s.w fa0, a0 -; RV32IF-ILP32F-NEXT: ret +; RV32IF-ILP32: # %bb.0: +; RV32IF-ILP32-NEXT: fcvt.s.w ft0, a0 %conv = sitofp i32 %a to float ret float %conv } |
