diff options
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/lib/CodeGen/RegisterCoalescer.cpp | 7 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/reg-coalescer-sched-crash.ll | 5 |
2 files changed, 8 insertions, 4 deletions
diff --git a/llvm/lib/CodeGen/RegisterCoalescer.cpp b/llvm/lib/CodeGen/RegisterCoalescer.cpp index 7855d2ba9bc..18cbad59ad4 100644 --- a/llvm/lib/CodeGen/RegisterCoalescer.cpp +++ b/llvm/lib/CodeGen/RegisterCoalescer.cpp @@ -1007,8 +1007,14 @@ bool RegisterCoalescer::reMaterializeTrivialDef(const CoalescerPair &CP, NewRC = TRI->getCommonSubClass(NewRC, DefRC); assert(NewRC && "subreg chosen for remat incompatible with instruction"); } + // Remap subranges to new lanemask and change register class. + LiveInterval &DstInt = LIS->getInterval(DstReg); + for (LiveInterval::SubRange &SR : DstInt.subranges()) { + SR.LaneMask = TRI->composeSubRegIndexLaneMask(DstIdx, SR.LaneMask); + } MRI->setRegClass(DstReg, NewRC); + // Update machine operands and add flags. updateRegDefsUses(DstReg, DstReg, DstIdx); NewMI->getOperand(0).setSubReg(NewIdx); // Add dead subregister definitions if we are defining the whole register @@ -1025,7 +1031,6 @@ bool RegisterCoalescer::reMaterializeTrivialDef(const CoalescerPair &CP, // // at this point for the part that wasn't defined before we could have // subranges missing the definition. - LiveInterval &DstInt = LIS->getInterval(DstReg); if (NewIdx == 0 && DstInt.hasSubRanges()) { SlotIndex CurrIdx = LIS->getInstructionIndex(*NewMI); SlotIndex DefIndex = CurrIdx.getRegSlot(NewMI->getOperand(0).isEarlyClobber()); diff --git a/llvm/test/CodeGen/AMDGPU/reg-coalescer-sched-crash.ll b/llvm/test/CodeGen/AMDGPU/reg-coalescer-sched-crash.ll index 2b7a4b22329..6e95f4c7521 100644 --- a/llvm/test/CodeGen/AMDGPU/reg-coalescer-sched-crash.ll +++ b/llvm/test/CodeGen/AMDGPU/reg-coalescer-sched-crash.ll @@ -1,6 +1,5 @@ -; XFAIL: * -; RUN: llc -march=amdgcn -verify-machineinstrs < %s -; XUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s +; RUN: llc -march=amdgcn -verify-machineinstrs -o /dev/null < %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs -o /dev/null < %s ; The register coalescer introduces a verifier error which later ; results in a crash during scheduling. |
