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-rw-r--r--llvm/lib/Target/AArch64/AArch64TargetMachine.cpp3
-rw-r--r--llvm/lib/Target/ARM/ARMTargetMachine.cpp3
-rw-r--r--llvm/lib/Target/X86/X86TargetMachine.cpp3
-rw-r--r--llvm/test/CodeGen/AArch64/macho-trap.ll7
-rw-r--r--llvm/test/CodeGen/ARM/fast-isel-shift-materialize.ll2
-rw-r--r--llvm/test/CodeGen/ARM/macho-trap.ll10
-rw-r--r--llvm/test/CodeGen/Thumb2/thumb2-ifcvt2.ll4
-rw-r--r--llvm/test/CodeGen/X86/avx512-fsel.ll1
-rw-r--r--llvm/test/CodeGen/X86/br-fold.ll3
-rw-r--r--llvm/test/CodeGen/X86/eh-frame-unreachable.ll1
-rw-r--r--llvm/test/CodeGen/X86/empty-functions.ll5
-rw-r--r--llvm/test/CodeGen/X86/macho-trap.ll7
-rw-r--r--llvm/test/CodeGen/X86/pr34421.ll2
-rw-r--r--llvm/test/MC/MachO/ARM/empty-function-nop.ll8
14 files changed, 47 insertions, 12 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
index 6a267ac7dbd..d7dea46a351 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
+++ b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
@@ -244,6 +244,9 @@ AArch64TargetMachine::AArch64TargetMachine(const Target &T, const Triple &TT,
TLOF(createTLOF(getTargetTriple())), isLittle(LittleEndian) {
initAsmInfo();
+ if (TT.isOSBinFormatMachO())
+ this->Options.TrapUnreachable = true;
+
// Enable GlobalISel at or below EnableGlobalISelAt0.
if (getOptLevel() <= EnableGlobalISelAtO)
setGlobalISel(true);
diff --git a/llvm/lib/Target/ARM/ARMTargetMachine.cpp b/llvm/lib/Target/ARM/ARMTargetMachine.cpp
index 83f281b98ed..9ed0851cf22 100644
--- a/llvm/lib/Target/ARM/ARMTargetMachine.cpp
+++ b/llvm/lib/Target/ARM/ARMTargetMachine.cpp
@@ -238,6 +238,9 @@ ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, const Triple &TT,
this->Options.EABIVersion = EABI::EABI5;
}
+ if (TT.isOSBinFormatMachO())
+ this->Options.TrapUnreachable = true;
+
initAsmInfo();
}
diff --git a/llvm/lib/Target/X86/X86TargetMachine.cpp b/llvm/lib/Target/X86/X86TargetMachine.cpp
index 87dadd9966c..2fbf6c3b4ae 100644
--- a/llvm/lib/Target/X86/X86TargetMachine.cpp
+++ b/llvm/lib/Target/X86/X86TargetMachine.cpp
@@ -224,7 +224,8 @@ X86TargetMachine::X86TargetMachine(const Target &T, const Triple &TT,
// The check here for 64-bit windows is a bit icky, but as we're unlikely
// to ever want to mix 32 and 64-bit windows code in a single module
// this should be fine.
- if ((TT.isOSWindows() && TT.getArch() == Triple::x86_64) || TT.isPS4())
+ if ((TT.isOSWindows() && TT.getArch() == Triple::x86_64) || TT.isPS4() ||
+ TT.isOSBinFormatMachO())
this->Options.TrapUnreachable = true;
initAsmInfo();
diff --git a/llvm/test/CodeGen/AArch64/macho-trap.ll b/llvm/test/CodeGen/AArch64/macho-trap.ll
new file mode 100644
index 00000000000..88700f837fe
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/macho-trap.ll
@@ -0,0 +1,7 @@
+; RUN: llc -mtriple=aarch64-apple-ios7.0 %s -o - | FileCheck %s
+
+define void @test_unreachable() {
+; CHECK-LABEL: test_unreachable:
+; CHECK: brk #0x1
+ unreachable
+}
diff --git a/llvm/test/CodeGen/ARM/fast-isel-shift-materialize.ll b/llvm/test/CodeGen/ARM/fast-isel-shift-materialize.ll
index ab36a979d71..6ecaaa99b83 100644
--- a/llvm/test/CodeGen/ARM/fast-isel-shift-materialize.ll
+++ b/llvm/test/CodeGen/ARM/fast-isel-shift-materialize.ll
@@ -19,7 +19,7 @@ bb:
%tmp4 = lshr i32 %tmp3, 2
%tmp10 = lshr i32 %tmp9, 2
call void @foo(i32 %tmp10, i32 %tmp4)
- unreachable
+ ret i32 undef
}
attributes #0 = { minsize }
diff --git a/llvm/test/CodeGen/ARM/macho-trap.ll b/llvm/test/CodeGen/ARM/macho-trap.ll
new file mode 100644
index 00000000000..34417aa88f5
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/macho-trap.ll
@@ -0,0 +1,10 @@
+; RUN: llc -mtriple=armv7-apple-ios7.0 %s -o - | FileCheck %s
+; RUN: llc -mtriple=thumbv7-apple-ios7.0 %s -o - | FileCheck %s
+; RUN: llc -mtriple=thumbv7m-apple-macho %s -o - | FileCheck %s
+; RUN: llc -mtriple=thumbv6m-apple-macho %s -o - | FileCheck %s
+
+define void @test_unreachable() {
+; CHECK-LABEL: test_unreachable:
+; CHECK: trap
+ unreachable
+}
diff --git a/llvm/test/CodeGen/Thumb2/thumb2-ifcvt2.ll b/llvm/test/CodeGen/Thumb2/thumb2-ifcvt2.ll
index 3c74dde1114..65a3aae4e9b 100644
--- a/llvm/test/CodeGen/Thumb2/thumb2-ifcvt2.ll
+++ b/llvm/test/CodeGen/Thumb2/thumb2-ifcvt2.ll
@@ -72,7 +72,7 @@ entry:
cond_true: ; preds = %entry
tail call void @abort( )
- unreachable
+ ret void
cond_false: ; preds = %entry
ret void
@@ -82,7 +82,7 @@ define fastcc void @t2() nounwind {
entry:
; CHECK-LABEL: t2:
; CHECK: cmp r0, #0
-; CHECK: %growMapping.exit
+; CHECK: trap
br i1 undef, label %bb.i.i3, label %growMapping.exit
bb.i.i3: ; preds = %entry
diff --git a/llvm/test/CodeGen/X86/avx512-fsel.ll b/llvm/test/CodeGen/X86/avx512-fsel.ll
index 0da690669c3..6efb66e6865 100644
--- a/llvm/test/CodeGen/X86/avx512-fsel.ll
+++ b/llvm/test/CodeGen/X86/avx512-fsel.ll
@@ -19,6 +19,7 @@ define i32 @test(float %a, float %b) {
; CHECK-NEXT: jmp LBB0_2
; CHECK-NEXT: LBB0_1: ## %L_0
; CHECK-NEXT: callq ___assert_rtn
+; CHECK-NEXT: ud2
; CHECK-NEXT: LBB0_2: ## %L_1
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: popq %rcx
diff --git a/llvm/test/CodeGen/X86/br-fold.ll b/llvm/test/CodeGen/X86/br-fold.ll
index d3aedbb17e7..074765b2ec7 100644
--- a/llvm/test/CodeGen/X86/br-fold.ll
+++ b/llvm/test/CodeGen/X86/br-fold.ll
@@ -5,8 +5,7 @@
; RUN: llc -mtriple=x86_64-scei-ps4 < %s | FileCheck -check-prefix=PS4 %s
; X64_DARWIN: orq
-; X64_DARWIN-NEXT: jne
-; X64_DARWIN-NEXT: %bb8.i329
+; X64-DARWIN-NEXT: ud2
; X64_LINUX: orq %rax, %rcx
; X64_LINUX-NEXT: jne
diff --git a/llvm/test/CodeGen/X86/eh-frame-unreachable.ll b/llvm/test/CodeGen/X86/eh-frame-unreachable.ll
index a7abc8a057f..7cdb06858a7 100644
--- a/llvm/test/CodeGen/X86/eh-frame-unreachable.ll
+++ b/llvm/test/CodeGen/X86/eh-frame-unreachable.ll
@@ -2,6 +2,7 @@
; Test that we don't emit a row that extends beyond the FDE's range_size.
;
; CHECK: movq %rsp, %rbp
+; CHECK: ud2
; CHECK-NEXT: .cfi_endproc
; CHECK-NOT: .cfi
diff --git a/llvm/test/CodeGen/X86/empty-functions.ll b/llvm/test/CodeGen/X86/empty-functions.ll
index 520acfb8d31..a310fb34078 100644
--- a/llvm/test/CodeGen/X86/empty-functions.ll
+++ b/llvm/test/CodeGen/X86/empty-functions.ll
@@ -11,7 +11,7 @@ entry:
; MachO cannot handle an empty function.
; CHECK-NO-FP: _func:
; CHECK-NO-FP-NEXT: .cfi_startproc
-; CHECK-NO-FP: nop
+; CHECK-NO-FP: ud2
; CHECK-NO-FP-NEXT: .cfi_endproc
; CHECK-FP: _func:
@@ -21,7 +21,8 @@ entry:
; CHECK-FP-NEXT: .cfi_def_cfa_offset 16
; CHECK-FP-NEXT: .cfi_offset %rbp, -16
; CHECK-FP-NEXT: movq %rsp, %rbp
-; CHECK-FP-NEXT: .cfi_endproc
+; CHECK-FP: ud2
+; CHECK-FP: .cfi_endproc
; An empty function is perfectly fine on ELF.
; LINUX-NO-FP: func:
diff --git a/llvm/test/CodeGen/X86/macho-trap.ll b/llvm/test/CodeGen/X86/macho-trap.ll
new file mode 100644
index 00000000000..630f5b38ca3
--- /dev/null
+++ b/llvm/test/CodeGen/X86/macho-trap.ll
@@ -0,0 +1,7 @@
+; RUN: llc -mtriple=x86_64-apple-macosx10.11 %s -o - | FileCheck %s
+
+define void @test_unreachable() {
+; CHECK-LABEL: test_unreachable:
+; CHECK: ud2
+ unreachable
+}
diff --git a/llvm/test/CodeGen/X86/pr34421.ll b/llvm/test/CodeGen/X86/pr34421.ll
index 8241410be36..a21191246c2 100644
--- a/llvm/test/CodeGen/X86/pr34421.ll
+++ b/llvm/test/CodeGen/X86/pr34421.ll
@@ -14,6 +14,7 @@ define void @thread_selfcounts() noimplicitfloat noredzone nounwind {
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp)
; X86-NEXT: movl %eax, {{[0-9]+}}(%esp)
+; X86-NEXT: ud2
; X86-NEXT: ## -- End function
;
; X64-LABEL: thread_selfcounts:
@@ -23,6 +24,7 @@ define void @thread_selfcounts() noimplicitfloat noredzone nounwind {
; X64-NEXT: movq {{[0-9]+}}(%rsp), %rcx
; X64-NEXT: movq %rax, (%rsp)
; X64-NEXT: movq %rcx, {{[0-9]+}}(%rsp)
+; X64-NEXT: ud2
; X64-NEXT: ## -- End function
entry:
%counts = alloca [2 x i64], align 16
diff --git a/llvm/test/MC/MachO/ARM/empty-function-nop.ll b/llvm/test/MC/MachO/ARM/empty-function-nop.ll
index 0bc439497e2..a2fc988c36e 100644
--- a/llvm/test/MC/MachO/ARM/empty-function-nop.ll
+++ b/llvm/test/MC/MachO/ARM/empty-function-nop.ll
@@ -10,14 +10,14 @@ define internal fastcc void @empty_function() {
unreachable
}
; CHECK-T1: SectionData (
-; CHECK-T1: 0000: C046 |.F|
+; CHECK-T1: 0000: FEDE |..|
; CHECK-T1: )
; CHECK-T2: SectionData (
-; CHECK-T2: 0000: 00BF |..|
+; CHECK-T2: 0000: FEDE |..|
; CHECK-T2: )
; CHECK-ARM: SectionData (
-; CHECK-ARM: 0000: 0000A0E1 |....|
+; CHECK-ARM: 0000: FEDEFFE7 |....|
; CHECK-ARM: )
; CHECK-ARMV7: SectionData (
-; CHECK-ARMV7: 0000: 00F020E3 |.. .|
+; CHECK-ARMV7: 0000: FEDEFFE7 |....|
; CHECK-ARMV7: )
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