3 files changed, 39 insertions, 12 deletions
diff --git a/llvm/lib/Target/X86/X86InstrSystem.td b/llvm/lib/Target/X86/X86InstrSystem.td
index 190f2958876..514a30c7dcc 100644
--- a/llvm/lib/Target/X86/X86InstrSystem.td
+++ b/llvm/lib/Target/X86/X86InstrSystem.td
@@ -359,15 +359,15 @@ def VERWm : I<0x00, MRM5m, (outs), (ins i16mem:$seg), "verw\t$seg", []>, TB;
 
 let SchedRW = [WriteSystem] in {
 def SGDT16m : I<0x01, MRM0m, (outs), (ins opaque48mem:$dst),
-                "sgdt{w}\t$dst", []>, TB, OpSize16, Requires<[Not64BitMode]>;
+                "sgdtw\t$dst", []>, TB, OpSize16, Requires<[Not64BitMode]>;
 def SGDT32m : I<0x01, MRM0m, (outs), (ins opaque48mem:$dst),
-                "sgdt{l}\t$dst", []>, OpSize32, TB, Requires <[Not64BitMode]>;
+                "sgdt{l|d}\t$dst", []>, OpSize32, TB, Requires <[Not64BitMode]>;
 def SGDT64m : I<0x01, MRM0m, (outs), (ins opaque80mem:$dst),
                 "sgdt{q}\t$dst", []>, TB, Requires <[In64BitMode]>;
 def SIDT16m : I<0x01, MRM1m, (outs), (ins opaque48mem:$dst),
-                "sidt{w}\t$dst", []>, TB, OpSize16, Requires<[Not64BitMode]>;
+                "sidtw\t$dst", []>, TB, OpSize16, Requires<[Not64BitMode]>;
 def SIDT32m : I<0x01, MRM1m, (outs), (ins opaque48mem:$dst),
-                "sidt{l}\t$dst", []>, OpSize32, TB, Requires <[Not64BitMode]>;
+                "sidt{l|d}\t$dst", []>, OpSize32, TB, Requires <[Not64BitMode]>;
 def SIDT64m : I<0x01, MRM1m, (outs), (ins opaque80mem:$dst),
                 "sidt{q}\t$dst", []>, TB, Requires <[In64BitMode]>;
 def SLDT16r : I<0x00, MRM0r, (outs GR16:$dst), (ins),
@@ -384,15 +384,15 @@ def SLDT64r : RI<0x00, MRM0r, (outs GR64:$dst), (ins),
                  "sldt{q}\t$dst", []>, TB, Requires<[In64BitMode]>;
 
 def LGDT16m : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
-                "lgdt{w}\t$src", []>, TB, OpSize16, Requires<[Not64BitMode]>;
+                "lgdtw\t$src", []>, TB, OpSize16, Requires<[Not64BitMode]>;
 def LGDT32m : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
-                "lgdt{l}\t$src", []>, OpSize32, TB, Requires<[Not64BitMode]>;
+                "lgdt{l|d}\t$src", []>, OpSize32, TB, Requires<[Not64BitMode]>;
 def LGDT64m : I<0x01, MRM2m, (outs), (ins opaque80mem:$src),
                 "lgdt{q}\t$src", []>, TB, Requires<[In64BitMode]>;
 def LIDT16m : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
-                "lidt{w}\t$src", []>, TB, OpSize16, Requires<[Not64BitMode]>;
+                "lidtw\t$src", []>, TB, OpSize16, Requires<[Not64BitMode]>;
 def LIDT32m : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
-                "lidt{l}\t$src", []>, OpSize32, TB, Requires<[Not64BitMode]>;
+                "lidt{l|d}\t$src", []>, OpSize32, TB, Requires<[Not64BitMode]>;
 def LIDT64m : I<0x01, MRM3m, (outs), (ins opaque80mem:$src),
                 "lidt{q}\t$src", []>, TB, Requires<[In64BitMode]>;
 def LLDT16r : I<0x00, MRM2r, (outs), (ins GR16:$src),
@@ -402,6 +402,15 @@ def LLDT16m : I<0x00, MRM2m, (outs), (ins i16mem:$src),
                 "lldt{w}\t$src", []>, TB;
 } // SchedRW
 
+def : InstAlias<"sgdt\t$dst", (SGDT16m opaque48mem:$dst), 0>, Requires<[In16BitMode]>;
+def : InstAlias<"sgdt\t$dst", (SGDT32m opaque48mem:$dst), 0>, Requires<[In32BitMode]>;
+def : InstAlias<"sidt\t$dst", (SIDT16m opaque48mem:$dst), 0>, Requires<[In16BitMode]>;
+def : InstAlias<"sidt\t$dst", (SIDT32m opaque48mem:$dst), 0>, Requires<[In32BitMode]>;
+def : InstAlias<"lgdt\t$src", (LGDT16m opaque48mem:$src), 0>, Requires<[In16BitMode]>;
+def : InstAlias<"lgdt\t$src", (LGDT32m opaque48mem:$src), 0>, Requires<[In32BitMode]>;
+def : InstAlias<"lidt\t$src", (LIDT16m opaque48mem:$src), 0>, Requires<[In16BitMode]>;
+def : InstAlias<"lidt\t$src", (LIDT32m opaque48mem:$src), 0>, Requires<[In32BitMode]>;
+
 //===----------------------------------------------------------------------===//
 // Specialized register support
 let SchedRW = [WriteSystem] in {
diff --git a/llvm/test/MC/Disassembler/X86/intel-syntax-32.txt b/llvm/test/MC/Disassembler/X86/intel-syntax-32.txt
index 66c87b8bc07..b47c8dbf0b6 100644
--- a/llvm/test/MC/Disassembler/X86/intel-syntax-32.txt
+++ b/llvm/test/MC/Disassembler/X86/intel-syntax-32.txt
@@ -1,15 +1,15 @@
 # RUN: llvm-mc --disassemble %s -triple=i386 --output-asm-variant=1 | FileCheck %s
 
-# CHECK: sgdt opaque ptr [eax]
+# CHECK: sgdtd opaque ptr [eax]
 0x0f 0x01 0x00
 
-# CHECK: sidt opaque ptr [eax]
+# CHECK: sidtd opaque ptr [eax]
 0x0f 0x01 0x08
 
-# CHECK: lgdt opaque ptr [eax]
+# CHECK: lgdtd opaque ptr [eax]
 0x0f 0x01 0x10
 
-# CHECK: lidt opaque ptr [eax]
+# CHECK: lidtd opaque ptr [eax]
 0x0f 0x01 0x18
 
 # CHECK: mov al, byte ptr [878082192]
diff --git a/llvm/test/MC/X86/intel-syntax-ptr-sized.s b/llvm/test/MC/X86/intel-syntax-ptr-sized.s
index c052c322b80..a360557eaa6 100644
--- a/llvm/test/MC/X86/intel-syntax-ptr-sized.s
+++ b/llvm/test/MC/X86/intel-syntax-ptr-sized.s
@@ -9,6 +9,15 @@ call [eax]
 jmp [eax]
 // CHECK: jmpl *(%eax)
 
+lgdt [eax]
+// CHECK: lgdtl (%eax)
+lidt [eax]
+// CHECK: lidtl (%eax)
+sgdt [eax]
+// CHECK: sgdtl (%eax)
+sidt [eax]
+// CHECK: sidtl (%eax)
+
 // mode switch
 .code16
 
@@ -18,3 +27,12 @@ call [eax]
 // CHECK: callw *(%eax)
 jmp [eax]
 // CHECK: jmpw *(%eax)
+
+lgdt [eax]
+// CHECK: lgdtw (%eax)
+lidt [eax]
+// CHECK: lidtw (%eax)
+sgdt [eax]
+// CHECK: sgdtw (%eax)
+sidt [eax]
+// CHECK: sidtw (%eax)