diff options
Diffstat (limited to 'llvm')
3 files changed, 19 insertions, 38 deletions
diff --git a/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td b/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td index 0727c9802e5..60fdf1c3dd3 100644 --- a/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td +++ b/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td @@ -26,4 +26,20 @@ class GINodeEquiv<Instruction i, SDNode node> { } def : GINodeEquiv<G_ADD, add>; +def : GINodeEquiv<G_SUB, sub>; +def : GINodeEquiv<G_MUL, mul>; + +def : GINodeEquiv<G_OR, or>; +def : GINodeEquiv<G_XOR, xor>; +def : GINodeEquiv<G_AND, and>; + +def : GINodeEquiv<G_SHL, shl>; +def : GINodeEquiv<G_LSHR, srl>; +def : GINodeEquiv<G_ASHR, sra>; + +def : GINodeEquiv<G_SDIV, sdiv>; +def : GINodeEquiv<G_UDIV, udiv>; +def : GINodeEquiv<G_SREM, srem>; +def : GINodeEquiv<G_UREM, urem>; + def : GINodeEquiv<G_BR, br>; diff --git a/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp index dea651631bd..5c03ea930af 100644 --- a/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp +++ b/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp @@ -126,57 +126,27 @@ static unsigned selectBinaryOp(unsigned GenericOpc, unsigned RegBankID, unsigned OpSize) { switch (RegBankID) { case AArch64::GPRRegBankID: - if (OpSize <= 32) { - assert((OpSize == 32 || (GenericOpc != TargetOpcode::G_SDIV && - GenericOpc != TargetOpcode::G_UDIV && - GenericOpc != TargetOpcode::G_LSHR && - GenericOpc != TargetOpcode::G_ASHR)) && - "operation should have been legalized before now"); - + if (OpSize == 32) { switch (GenericOpc) { - case TargetOpcode::G_OR: - return AArch64::ORRWrr; - case TargetOpcode::G_XOR: - return AArch64::EORWrr; - case TargetOpcode::G_AND: - return AArch64::ANDWrr; - case TargetOpcode::G_SUB: - return AArch64::SUBWrr; case TargetOpcode::G_SHL: return AArch64::LSLVWr; case TargetOpcode::G_LSHR: return AArch64::LSRVWr; case TargetOpcode::G_ASHR: return AArch64::ASRVWr; - case TargetOpcode::G_SDIV: - return AArch64::SDIVWr; - case TargetOpcode::G_UDIV: - return AArch64::UDIVWr; default: return GenericOpc; } } else if (OpSize == 64) { switch (GenericOpc) { - case TargetOpcode::G_OR: - return AArch64::ORRXrr; - case TargetOpcode::G_XOR: - return AArch64::EORXrr; - case TargetOpcode::G_AND: - return AArch64::ANDXrr; case TargetOpcode::G_GEP: return AArch64::ADDXrr; - case TargetOpcode::G_SUB: - return AArch64::SUBXrr; case TargetOpcode::G_SHL: return AArch64::LSLVXr; case TargetOpcode::G_LSHR: return AArch64::LSRVXr; case TargetOpcode::G_ASHR: return AArch64::ASRVXr; - case TargetOpcode::G_SDIV: - return AArch64::SDIVXr; - case TargetOpcode::G_UDIV: - return AArch64::UDIVXr; default: return GenericOpc; } @@ -749,14 +719,9 @@ bool AArch64InstructionSelector::select(MachineInstr &I) const { case TargetOpcode::G_FDIV: case TargetOpcode::G_OR: - case TargetOpcode::G_XOR: - case TargetOpcode::G_AND: case TargetOpcode::G_SHL: case TargetOpcode::G_LSHR: case TargetOpcode::G_ASHR: - case TargetOpcode::G_SDIV: - case TargetOpcode::G_UDIV: - case TargetOpcode::G_SUB: case TargetOpcode::G_GEP: { // Reject the various things we don't support yet. if (unsupportedBinOp(I, RBI, MRI, TRI)) diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir index eb7827fd74b..0d51462aad2 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir @@ -220,7 +220,7 @@ registers: # CHECK: body: # CHECK: %0 = COPY %w0 # CHECK: %1 = COPY %w1 -# CHECK: %2 = SUBWrr %0, %1 +# CHECK: %2 = SUBSWrr %0, %1 body: | bb.0: liveins: %w0, %w1 @@ -249,7 +249,7 @@ registers: # CHECK: body: # CHECK: %0 = COPY %x0 # CHECK: %1 = COPY %x1 -# CHECK: %2 = SUBXrr %0, %1 +# CHECK: %2 = SUBSXrr %0, %1 body: | bb.0: liveins: %x0, %x1 |
