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-rw-r--r--llvm/utils/TableGen/AsmWriterEmitter.cpp8
-rw-r--r--llvm/utils/TableGen/CodeGenSchedule.cpp14
-rw-r--r--llvm/utils/TableGen/FixedLenDecoderEmitter.cpp8
-rw-r--r--llvm/utils/TableGen/SubtargetEmitter.cpp8
4 files changed, 11 insertions, 27 deletions
diff --git a/llvm/utils/TableGen/AsmWriterEmitter.cpp b/llvm/utils/TableGen/AsmWriterEmitter.cpp
index fc2138f7e8e..e80b0db31c4 100644
--- a/llvm/utils/TableGen/AsmWriterEmitter.cpp
+++ b/llvm/utils/TableGen/AsmWriterEmitter.cpp
@@ -157,8 +157,7 @@ FindUniqueOperandCommands(std::vector<std::string> &UniqueOperandCommands,
// Check to see if we already have 'Command' in UniqueOperandCommands.
// If not, add it.
- auto I = std::find(UniqueOperandCommands.begin(),
- UniqueOperandCommands.end(), Command);
+ auto I = find(UniqueOperandCommands, Command);
if (I != UniqueOperandCommands.end()) {
size_t idx = I - UniqueOperandCommands.begin();
InstrsForCase[idx] += ", ";
@@ -838,9 +837,8 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) {
Rec->isSubClassOf("Operand")) {
std::string PrintMethod = Rec->getValueAsString("PrintMethod");
if (PrintMethod != "" && PrintMethod != "printOperand") {
- PrintMethodIdx = std::find(PrintMethods.begin(),
- PrintMethods.end(), PrintMethod) -
- PrintMethods.begin();
+ PrintMethodIdx =
+ find(PrintMethods, PrintMethod) - PrintMethods.begin();
if (static_cast<unsigned>(PrintMethodIdx) == PrintMethods.size())
PrintMethods.push_back(PrintMethod);
}
diff --git a/llvm/utils/TableGen/CodeGenSchedule.cpp b/llvm/utils/TableGen/CodeGenSchedule.cpp
index d6b5e0a90eb..22f48ad3d48 100644
--- a/llvm/utils/TableGen/CodeGenSchedule.cpp
+++ b/llvm/utils/TableGen/CodeGenSchedule.cpp
@@ -1498,9 +1498,7 @@ void CodeGenSchedModels::collectProcResources() {
if (!(*RI)->getValueInit("SchedModel")->isComplete())
continue;
CodeGenProcModel &PM = getProcModel((*RI)->getValueAsDef("SchedModel"));
- RecIter I = std::find(PM.ProcResourceDefs.begin(),
- PM.ProcResourceDefs.end(), *RI);
- if (I == PM.ProcResourceDefs.end())
+ if (!is_contained(PM.ProcResourceDefs, *RI))
PM.ProcResourceDefs.push_back(*RI);
}
// Finalize each ProcModel by sorting the record arrays.
@@ -1716,9 +1714,7 @@ void CodeGenSchedModels::addProcResource(Record *ProcResKind,
Record *ProcResUnits = findProcResUnits(ProcResKind, PM);
// See if this ProcResource is already associated with this processor.
- RecIter I = std::find(PM.ProcResourceDefs.begin(),
- PM.ProcResourceDefs.end(), ProcResUnits);
- if (I != PM.ProcResourceDefs.end())
+ if (is_contained(PM.ProcResourceDefs, ProcResUnits))
return;
PM.ProcResourceDefs.push_back(ProcResUnits);
@@ -1737,8 +1733,7 @@ void CodeGenSchedModels::addWriteRes(Record *ProcWriteResDef, unsigned PIdx) {
assert(PIdx && "don't add resources to an invalid Processor model");
RecVec &WRDefs = ProcModels[PIdx].WriteResDefs;
- RecIter WRI = find(WRDefs, ProcWriteResDef);
- if (WRI != WRDefs.end())
+ if (is_contained(WRDefs, ProcWriteResDef))
return;
WRDefs.push_back(ProcWriteResDef);
@@ -1754,8 +1749,7 @@ void CodeGenSchedModels::addWriteRes(Record *ProcWriteResDef, unsigned PIdx) {
void CodeGenSchedModels::addReadAdvance(Record *ProcReadAdvanceDef,
unsigned PIdx) {
RecVec &RADefs = ProcModels[PIdx].ReadAdvanceDefs;
- RecIter I = find(RADefs, ProcReadAdvanceDef);
- if (I != RADefs.end())
+ if (is_contained(RADefs, ProcReadAdvanceDef))
return;
RADefs.push_back(ProcReadAdvanceDef);
}
diff --git a/llvm/utils/TableGen/FixedLenDecoderEmitter.cpp b/llvm/utils/TableGen/FixedLenDecoderEmitter.cpp
index 1200324d6b0..733c7549b2c 100644
--- a/llvm/utils/TableGen/FixedLenDecoderEmitter.cpp
+++ b/llvm/utils/TableGen/FixedLenDecoderEmitter.cpp
@@ -1108,9 +1108,7 @@ unsigned FilterChooser::getDecoderIndex(DecoderSet &Decoders,
// Make sure the predicate is in the table.
Decoders.insert(StringRef(Decoder));
// Now figure out the index for when we write out the table.
- DecoderSet::const_iterator P = std::find(Decoders.begin(),
- Decoders.end(),
- Decoder.str());
+ DecoderSet::const_iterator P = find(Decoders, Decoder.str());
return (unsigned)(P - Decoders.begin());
}
@@ -1183,9 +1181,7 @@ unsigned FilterChooser::getPredicateIndex(DecoderTableInfo &TableInfo,
// Make sure the predicate is in the table.
TableInfo.Predicates.insert(Predicate.str());
// Now figure out the index for when we write out the table.
- PredicateSet::const_iterator P = std::find(TableInfo.Predicates.begin(),
- TableInfo.Predicates.end(),
- Predicate.str());
+ PredicateSet::const_iterator P = find(TableInfo.Predicates, Predicate.str());
return (unsigned)(P - TableInfo.Predicates.begin());
}
diff --git a/llvm/utils/TableGen/SubtargetEmitter.cpp b/llvm/utils/TableGen/SubtargetEmitter.cpp
index bc56384d2fa..9719412d8ee 100644
--- a/llvm/utils/TableGen/SubtargetEmitter.cpp
+++ b/llvm/utils/TableGen/SubtargetEmitter.cpp
@@ -826,9 +826,7 @@ void SubtargetEmitter::GenSchedClassTables(const CodeGenProcModel &ProcModel,
HasVariants = true;
break;
}
- IdxIter PIPos = std::find(TI->ProcIndices.begin(),
- TI->ProcIndices.end(), ProcModel.Index);
- if (PIPos != TI->ProcIndices.end()) {
+ if (is_contained(TI->ProcIndices, ProcModel.Index)) {
HasVariants = true;
break;
}
@@ -843,9 +841,7 @@ void SubtargetEmitter::GenSchedClassTables(const CodeGenProcModel &ProcModel,
// If ProcIndices contains 0, this class applies to all processors.
assert(!SC.ProcIndices.empty() && "expect at least one procidx");
if (SC.ProcIndices[0] != 0) {
- IdxIter PIPos = std::find(SC.ProcIndices.begin(),
- SC.ProcIndices.end(), ProcModel.Index);
- if (PIPos == SC.ProcIndices.end())
+ if (!is_contained(SC.ProcIndices, ProcModel.Index))
continue;
}
IdxVec Writes = SC.Writes;
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