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-rw-r--r--llvm/utils/TableGen/CTagsEmitter.cpp2
-rw-r--r--llvm/utils/TableGen/CodeGenDAGPatterns.cpp4
-rw-r--r--llvm/utils/TableGen/CodeGenRegisters.cpp14
-rw-r--r--llvm/utils/TableGen/CodeGenSchedule.cpp14
-rw-r--r--llvm/utils/TableGen/CodeGenTarget.cpp10
-rw-r--r--llvm/utils/TableGen/GlobalISelEmitter.cpp10
-rw-r--r--llvm/utils/TableGen/InfoByHwMode.cpp4
-rw-r--r--llvm/utils/TableGen/SubtargetEmitter.cpp17
8 files changed, 37 insertions, 38 deletions
diff --git a/llvm/utils/TableGen/CTagsEmitter.cpp b/llvm/utils/TableGen/CTagsEmitter.cpp
index a0f83f1c991..bd596bcb47a 100644
--- a/llvm/utils/TableGen/CTagsEmitter.cpp
+++ b/llvm/utils/TableGen/CTagsEmitter.cpp
@@ -73,7 +73,7 @@ void CTagsEmitter::run(raw_ostream &OS) {
for (const auto &D : Defs)
Tags.push_back(Tag(D.first, locate(D.second.get())));
// Emit tags.
- llvm::sort(Tags.begin(), Tags.end());
+ llvm::sort(Tags);
OS << "!_TAG_FILE_FORMAT\t1\t/original ctags format/\n";
OS << "!_TAG_FILE_SORTED\t1\t/0=unsorted, 1=sorted, 2=foldcase/\n";
for (const Tag &T : Tags)
diff --git a/llvm/utils/TableGen/CodeGenDAGPatterns.cpp b/llvm/utils/TableGen/CodeGenDAGPatterns.cpp
index 4a409f173d6..ed68b09c265 100644
--- a/llvm/utils/TableGen/CodeGenDAGPatterns.cpp
+++ b/llvm/utils/TableGen/CodeGenDAGPatterns.cpp
@@ -1318,7 +1318,7 @@ std::string PatternToMatch::getPredicateCheck() const {
SmallVector<const Predicate*,4> PredList;
for (const Predicate &P : Predicates)
PredList.push_back(&P);
- llvm::sort(PredList.begin(), PredList.end(), deref<llvm::less>());
+ llvm::sort(PredList, deref<llvm::less>());
std::string Check;
for (unsigned i = 0, e = PredList.size(); i != e; ++i) {
@@ -3742,7 +3742,7 @@ std::vector<Predicate> CodeGenDAGPatterns::makePredList(ListInit *L) {
}
// Sort so that different orders get canonicalized to the same string.
- llvm::sort(Preds.begin(), Preds.end());
+ llvm::sort(Preds);
return Preds;
}
diff --git a/llvm/utils/TableGen/CodeGenRegisters.cpp b/llvm/utils/TableGen/CodeGenRegisters.cpp
index b0d13b7d38f..e70a79f08af 100644
--- a/llvm/utils/TableGen/CodeGenRegisters.cpp
+++ b/llvm/utils/TableGen/CodeGenRegisters.cpp
@@ -725,7 +725,7 @@ struct TupleExpander : SetTheory::Expander {
//===----------------------------------------------------------------------===//
static void sortAndUniqueRegisters(CodeGenRegister::Vec &M) {
- llvm::sort(M.begin(), M.end(), deref<llvm::less>());
+ llvm::sort(M, deref<llvm::less>());
M.erase(std::unique(M.begin(), M.end(), deref<llvm::equal>()), M.end());
}
@@ -997,7 +997,7 @@ CodeGenRegisterClass::getMatchingSubClassWithSubRegs(
for (auto &RC : RegClasses)
if (SuperRegRCsBV[RC.EnumValue])
SuperRegRCs.emplace_back(&RC);
- llvm::sort(SuperRegRCs.begin(), SuperRegRCs.end(), SizeOrder);
+ llvm::sort(SuperRegRCs, SizeOrder);
assert(SuperRegRCs.front() == BiggestSuperRegRC && "Biggest class wasn't first");
// Find all the subreg classes and order them by size too.
@@ -1008,7 +1008,7 @@ CodeGenRegisterClass::getMatchingSubClassWithSubRegs(
if (SuperRegClassesBV.any())
SuperRegClasses.push_back(std::make_pair(&RC, SuperRegClassesBV));
}
- llvm::sort(SuperRegClasses.begin(), SuperRegClasses.end(),
+ llvm::sort(SuperRegClasses,
[&](const std::pair<CodeGenRegisterClass *, BitVector> &A,
const std::pair<CodeGenRegisterClass *, BitVector> &B) {
return SizeOrder(A.first, B.first);
@@ -1073,7 +1073,7 @@ void CodeGenRegisterClass::buildRegUnitSet(const CodeGenRegBank &RegBank,
if (!RU.Artificial)
TmpUnits.push_back(*UnitI);
}
- llvm::sort(TmpUnits.begin(), TmpUnits.end());
+ llvm::sort(TmpUnits);
std::unique_copy(TmpUnits.begin(), TmpUnits.end(),
std::back_inserter(RegUnits));
}
@@ -1093,7 +1093,7 @@ CodeGenRegBank::CodeGenRegBank(RecordKeeper &Records,
// Read in the user-defined (named) sub-register indices.
// More indices will be synthesized later.
std::vector<Record*> SRIs = Records.getAllDerivedDefinitions("SubRegIndex");
- llvm::sort(SRIs.begin(), SRIs.end(), LessRecord());
+ llvm::sort(SRIs, LessRecord());
for (unsigned i = 0, e = SRIs.size(); i != e; ++i)
getSubRegIdx(SRIs[i]);
// Build composite maps from ComposedOf fields.
@@ -1102,7 +1102,7 @@ CodeGenRegBank::CodeGenRegBank(RecordKeeper &Records,
// Read in the register definitions.
std::vector<Record*> Regs = Records.getAllDerivedDefinitions("Register");
- llvm::sort(Regs.begin(), Regs.end(), LessRecordRegister());
+ llvm::sort(Regs, LessRecordRegister());
// Assign the enumeration values.
for (unsigned i = 0, e = Regs.size(); i != e; ++i)
getReg(Regs[i]);
@@ -1113,7 +1113,7 @@ CodeGenRegBank::CodeGenRegBank(RecordKeeper &Records,
for (Record *R : Tups) {
std::vector<Record *> TupRegs = *Sets.expand(R);
- llvm::sort(TupRegs.begin(), TupRegs.end(), LessRecordRegister());
+ llvm::sort(TupRegs, LessRecordRegister());
for (Record *RC : TupRegs)
getReg(RC);
}
diff --git a/llvm/utils/TableGen/CodeGenSchedule.cpp b/llvm/utils/TableGen/CodeGenSchedule.cpp
index 625944bcfe9..57b59108528 100644
--- a/llvm/utils/TableGen/CodeGenSchedule.cpp
+++ b/llvm/utils/TableGen/CodeGenSchedule.cpp
@@ -365,7 +365,7 @@ processSTIPredicate(STIPredicateFunction &Fn,
// Sort OpcodeMappings elements based on their CPU and predicate masks.
// As a last resort, order elements by opcode identifier.
- llvm::sort(OpcodeMappings.begin(), OpcodeMappings.end(),
+ llvm::sort(OpcodeMappings,
[&](const OpcodeMapPair &Lhs, const OpcodeMapPair &Rhs) {
unsigned LhsIdx = Opcode2Index[Lhs.first];
unsigned RhsIdx = Opcode2Index[Rhs.first];
@@ -496,7 +496,7 @@ void CodeGenSchedModels::collectOptionalProcessorInfo() {
/// Gather all processor models.
void CodeGenSchedModels::collectProcModels() {
RecVec ProcRecords = Records.getAllDerivedDefinitions("Processor");
- llvm::sort(ProcRecords.begin(), ProcRecords.end(), LessRecordFieldName());
+ llvm::sort(ProcRecords, LessRecordFieldName());
// Reserve space because we can. Reallocation would be ok.
ProcModels.reserve(ProcRecords.size()+1);
@@ -615,7 +615,7 @@ void CodeGenSchedModels::collectSchedRW() {
// Find all ReadWrites referenced by SchedAlias. AliasDefs needs to be sorted
// for the loop below that initializes Alias vectors.
RecVec AliasDefs = Records.getAllDerivedDefinitions("SchedAlias");
- llvm::sort(AliasDefs.begin(), AliasDefs.end(), LessRecord());
+ llvm::sort(AliasDefs, LessRecord());
for (Record *ADef : AliasDefs) {
Record *MatchDef = ADef->getValueAsDef("MatchRW");
Record *AliasDef = ADef->getValueAsDef("AliasRW");
@@ -633,12 +633,12 @@ void CodeGenSchedModels::collectSchedRW() {
}
// Sort and add the SchedReadWrites directly referenced by instructions or
// itinerary resources. Index reads and writes in separate domains.
- llvm::sort(SWDefs.begin(), SWDefs.end(), LessRecord());
+ llvm::sort(SWDefs, LessRecord());
for (Record *SWDef : SWDefs) {
assert(!getSchedRWIdx(SWDef, /*IsRead=*/false) && "duplicate SchedWrite");
SchedWrites.emplace_back(SchedWrites.size(), SWDef);
}
- llvm::sort(SRDefs.begin(), SRDefs.end(), LessRecord());
+ llvm::sort(SRDefs, LessRecord());
for (Record *SRDef : SRDefs) {
assert(!getSchedRWIdx(SRDef, /*IsRead-*/true) && "duplicate SchedWrite");
SchedReads.emplace_back(SchedReads.size(), SRDef);
@@ -858,7 +858,7 @@ void CodeGenSchedModels::collectSchedClasses() {
}
// Create classes for InstRW defs.
RecVec InstRWDefs = Records.getAllDerivedDefinitions("InstRW");
- llvm::sort(InstRWDefs.begin(), InstRWDefs.end(), LessRecord());
+ llvm::sort(InstRWDefs, LessRecord());
LLVM_DEBUG(dbgs() << "\n+++ SCHED CLASSES (createInstRWClass) +++\n");
for (Record *RWDef : InstRWDefs)
createInstRWClass(RWDef);
@@ -1162,7 +1162,7 @@ void CodeGenSchedModels::collectProcItins() {
// Gather the read/write types for each itinerary class.
void CodeGenSchedModels::collectProcItinRW() {
RecVec ItinRWDefs = Records.getAllDerivedDefinitions("ItinRW");
- llvm::sort(ItinRWDefs.begin(), ItinRWDefs.end(), LessRecord());
+ llvm::sort(ItinRWDefs, LessRecord());
for (Record *RWDef : ItinRWDefs) {
if (!RWDef->getValueInit("SchedModel")->isComplete())
PrintFatalError(RWDef->getLoc(), "SchedModel is undefined");
diff --git a/llvm/utils/TableGen/CodeGenTarget.cpp b/llvm/utils/TableGen/CodeGenTarget.cpp
index cb73ca83c9b..2766fcca161 100644
--- a/llvm/utils/TableGen/CodeGenTarget.cpp
+++ b/llvm/utils/TableGen/CodeGenTarget.cpp
@@ -278,7 +278,7 @@ CodeGenRegBank &CodeGenTarget::getRegBank() const {
void CodeGenTarget::ReadRegAltNameIndices() const {
RegAltNameIndices = Records.getAllDerivedDefinitions("RegAltNameIndex");
- llvm::sort(RegAltNameIndices.begin(), RegAltNameIndices.end(), LessRecord());
+ llvm::sort(RegAltNameIndices, LessRecord());
}
/// getRegisterByName - If there is a register with the specific AsmName,
@@ -303,7 +303,7 @@ std::vector<ValueTypeByHwMode> CodeGenTarget::getRegisterVTs(Record *R)
}
// Remove duplicates.
- llvm::sort(Result.begin(), Result.end());
+ llvm::sort(Result);
Result.erase(std::unique(Result.begin(), Result.end()), Result.end());
return Result;
}
@@ -314,7 +314,7 @@ void CodeGenTarget::ReadLegalValueTypes() const {
LegalValueTypes.insert(LegalValueTypes.end(), RC.VTs.begin(), RC.VTs.end());
// Remove duplicates.
- llvm::sort(LegalValueTypes.begin(), LegalValueTypes.end());
+ llvm::sort(LegalValueTypes);
LegalValueTypes.erase(std::unique(LegalValueTypes.begin(),
LegalValueTypes.end()),
LegalValueTypes.end());
@@ -513,7 +513,7 @@ CodeGenIntrinsicTable::CodeGenIntrinsicTable(const RecordKeeper &RC,
if (isTarget == TargetOnly)
Intrinsics.push_back(CodeGenIntrinsic(Defs[I]));
}
- llvm::sort(Intrinsics.begin(), Intrinsics.end(),
+ llvm::sort(Intrinsics,
[](const CodeGenIntrinsic &LHS, const CodeGenIntrinsic &RHS) {
return std::tie(LHS.TargetPrefix, LHS.Name) <
std::tie(RHS.TargetPrefix, RHS.Name);
@@ -709,6 +709,6 @@ CodeGenIntrinsic::CodeGenIntrinsic(Record *R) {
Properties = parseSDPatternOperatorProperties(R);
// Sort the argument attributes for later benefit.
- llvm::sort(ArgumentAttributes.begin(), ArgumentAttributes.end());
+ llvm::sort(ArgumentAttributes);
}
diff --git a/llvm/utils/TableGen/GlobalISelEmitter.cpp b/llvm/utils/TableGen/GlobalISelEmitter.cpp
index 03e2f381d9c..18a3afeb453 100644
--- a/llvm/utils/TableGen/GlobalISelEmitter.cpp
+++ b/llvm/utils/TableGen/GlobalISelEmitter.cpp
@@ -2613,7 +2613,7 @@ public:
std::vector<unsigned> MergeInsnIDs;
for (const auto &IDMatcherPair : Rule.defined_insn_vars())
MergeInsnIDs.push_back(IDMatcherPair.second);
- llvm::sort(MergeInsnIDs.begin(), MergeInsnIDs.end());
+ llvm::sort(MergeInsnIDs);
for (const auto &MergeInsnID : MergeInsnIDs)
Table << MatchTable::IntValue(MergeInsnID);
Table << MatchTable::NamedValue("GIU_MergeMemOperands_EndOfList")
@@ -2812,7 +2812,7 @@ void RuleMatcher::emit(MatchTable &Table) {
InsnIDs.push_back(Pair.second);
}
- llvm::sort(InsnIDs.begin(), InsnIDs.end());
+ llvm::sort(InsnIDs);
for (const auto &InsnID : InsnIDs) {
// Reject the difficult cases until we have a more accurate check.
@@ -4288,11 +4288,11 @@ void GlobalISelEmitter::run(raw_ostream &OS) {
std::vector<Record *> ComplexPredicates =
RK.getAllDerivedDefinitions("GIComplexOperandMatcher");
- llvm::sort(ComplexPredicates.begin(), ComplexPredicates.end(), orderByName);
+ llvm::sort(ComplexPredicates, orderByName);
std::vector<Record *> CustomRendererFns =
RK.getAllDerivedDefinitions("GICustomOperandRenderer");
- llvm::sort(CustomRendererFns.begin(), CustomRendererFns.end(), orderByName);
+ llvm::sort(CustomRendererFns, orderByName);
unsigned MaxTemporaries = 0;
for (const auto &Rule : Rules)
@@ -4371,7 +4371,7 @@ void GlobalISelEmitter::run(raw_ostream &OS) {
std::vector<LLTCodeGen> TypeObjects;
for (const auto &Ty : KnownTypes)
TypeObjects.push_back(Ty);
- llvm::sort(TypeObjects.begin(), TypeObjects.end());
+ llvm::sort(TypeObjects);
OS << "// LLT Objects.\n"
<< "enum {\n";
for (const auto &TypeObject : TypeObjects) {
diff --git a/llvm/utils/TableGen/InfoByHwMode.cpp b/llvm/utils/TableGen/InfoByHwMode.cpp
index 7d1f71cc264..086e12dafd7 100644
--- a/llvm/utils/TableGen/InfoByHwMode.cpp
+++ b/llvm/utils/TableGen/InfoByHwMode.cpp
@@ -84,7 +84,7 @@ void ValueTypeByHwMode::writeToStream(raw_ostream &OS) const {
std::vector<const PairType*> Pairs;
for (const auto &P : Map)
Pairs.push_back(&P);
- llvm::sort(Pairs.begin(), Pairs.end(), deref<std::less<PairType>>());
+ llvm::sort(Pairs, deref<std::less<PairType>>());
OS << '{';
for (unsigned i = 0, e = Pairs.size(); i != e; ++i) {
@@ -176,7 +176,7 @@ void RegSizeInfoByHwMode::writeToStream(raw_ostream &OS) const {
std::vector<const PairType*> Pairs;
for (const auto &P : Map)
Pairs.push_back(&P);
- llvm::sort(Pairs.begin(), Pairs.end(), deref<std::less<PairType>>());
+ llvm::sort(Pairs, deref<std::less<PairType>>());
OS << '{';
for (unsigned i = 0, e = Pairs.size(); i != e; ++i) {
diff --git a/llvm/utils/TableGen/SubtargetEmitter.cpp b/llvm/utils/TableGen/SubtargetEmitter.cpp
index 100399f52ff..ef0428eeed0 100644
--- a/llvm/utils/TableGen/SubtargetEmitter.cpp
+++ b/llvm/utils/TableGen/SubtargetEmitter.cpp
@@ -140,7 +140,7 @@ void SubtargetEmitter::Enumeration(raw_ostream &OS) {
// Get all records of class and sort
std::vector<Record*> DefList =
Records.getAllDerivedDefinitions("SubtargetFeature");
- llvm::sort(DefList.begin(), DefList.end(), LessRecord());
+ llvm::sort(DefList, LessRecord());
unsigned N = DefList.size();
if (N == 0)
@@ -179,7 +179,7 @@ unsigned SubtargetEmitter::FeatureKeyValues(raw_ostream &OS) {
if (FeatureList.empty())
return 0;
- llvm::sort(FeatureList.begin(), FeatureList.end(), LessRecordFieldName());
+ llvm::sort(FeatureList, LessRecordFieldName());
// Begin feature table
OS << "// Sorted (by key) array of values for CPU features.\n"
@@ -229,7 +229,7 @@ unsigned SubtargetEmitter::CPUKeyValues(raw_ostream &OS) {
// Gather and sort processor information
std::vector<Record*> ProcessorList =
Records.getAllDerivedDefinitions("Processor");
- llvm::sort(ProcessorList.begin(), ProcessorList.end(), LessRecordFieldName());
+ llvm::sort(ProcessorList, LessRecordFieldName());
// Begin processor table
OS << "// Sorted (by key) array of values for CPU subtype.\n"
@@ -1182,7 +1182,7 @@ void SubtargetEmitter::GenSchedClassTables(const CodeGenProcModel &ProcModel,
WriteIDs.push_back(SchedModels.getSchedRWIdx(VW, /*IsRead=*/false));
}
}
- llvm::sort(WriteIDs.begin(), WriteIDs.end());
+ llvm::sort(WriteIDs);
for(unsigned W : WriteIDs) {
MCReadAdvanceEntry RAEntry;
RAEntry.UseIdx = UseIdx;
@@ -1200,8 +1200,7 @@ void SubtargetEmitter::GenSchedClassTables(const CodeGenProcModel &ProcModel,
// compression.
//
// WritePrecRes entries are sorted by ProcResIdx.
- llvm::sort(WriteProcResources.begin(), WriteProcResources.end(),
- LessWriteProcResources());
+ llvm::sort(WriteProcResources, LessWriteProcResources());
SCDesc.NumWriteProcResEntries = WriteProcResources.size();
std::vector<MCWriteProcResEntry>::iterator WPRPos =
@@ -1413,7 +1412,7 @@ void SubtargetEmitter::EmitProcessorLookup(raw_ostream &OS) {
// Gather and sort processor information
std::vector<Record*> ProcessorList =
Records.getAllDerivedDefinitions("Processor");
- llvm::sort(ProcessorList.begin(), ProcessorList.end(), LessRecordFieldName());
+ llvm::sort(ProcessorList, LessRecordFieldName());
// Begin processor table
OS << "\n";
@@ -1479,7 +1478,7 @@ static void emitPredicateProlog(const RecordKeeper &Records, raw_ostream &OS) {
// stream.
std::vector<Record *> Prologs =
Records.getAllDerivedDefinitions("PredicateProlog");
- llvm::sort(Prologs.begin(), Prologs.end(), LessRecord());
+ llvm::sort(Prologs, LessRecord());
for (Record *P : Prologs)
Stream << P->getValueAsString("Code") << '\n';
@@ -1717,7 +1716,7 @@ void SubtargetEmitter::ParseFeaturesFunction(raw_ostream &OS,
unsigned NumProcs) {
std::vector<Record*> Features =
Records.getAllDerivedDefinitions("SubtargetFeature");
- llvm::sort(Features.begin(), Features.end(), LessRecord());
+ llvm::sort(Features, LessRecord());
OS << "// ParseSubtargetFeatures - Parses features string setting specified\n"
<< "// subtarget options.\n"
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