summaryrefslogtreecommitdiffstats
path: root/llvm/utils/TableGen/X86FoldTablesEmitter.cpp
diff options
context:
space:
mode:
Diffstat (limited to 'llvm/utils/TableGen/X86FoldTablesEmitter.cpp')
-rw-r--r--llvm/utils/TableGen/X86FoldTablesEmitter.cpp6
1 files changed, 3 insertions, 3 deletions
diff --git a/llvm/utils/TableGen/X86FoldTablesEmitter.cpp b/llvm/utils/TableGen/X86FoldTablesEmitter.cpp
index 2c15e35f234..8026c324cd4 100644
--- a/llvm/utils/TableGen/X86FoldTablesEmitter.cpp
+++ b/llvm/utils/TableGen/X86FoldTablesEmitter.cpp
@@ -618,14 +618,14 @@ void X86FoldTablesEmitter::run(formatted_raw_ostream &OS) {
uint8_t Opc =
getValueFromBitsInit(MemInst->TheDef->getValueAsBitsInit("Opcode"));
- if (RegInsts.count(Opc) == 0)
+ auto RegInstsIt = RegInsts.find(Opc);
+ if (RegInstsIt == RegInsts.end())
continue;
// Two forms (memory & register) of the same instruction must have the same
// opcode. try matching only with register form instructions with the same
// opcode.
- std::vector<const CodeGenInstruction *> &OpcRegInsts =
- RegInsts.find(Opc)->second;
+ std::vector<const CodeGenInstruction *> &OpcRegInsts = RegInstsIt->second;
auto Match = find_if(OpcRegInsts, IsMatch(MemInst, Records));
if (Match != OpcRegInsts.end()) {
OpenPOWER on IntegriCloud