diff options
Diffstat (limited to 'llvm/unittests/tools/llvm-exegesis/Mips/TargetTest.cpp')
| -rw-r--r-- | llvm/unittests/tools/llvm-exegesis/Mips/TargetTest.cpp | 65 |
1 files changed, 60 insertions, 5 deletions
diff --git a/llvm/unittests/tools/llvm-exegesis/Mips/TargetTest.cpp b/llvm/unittests/tools/llvm-exegesis/Mips/TargetTest.cpp index 16c8e5fda27..2509beb26d7 100644 --- a/llvm/unittests/tools/llvm-exegesis/Mips/TargetTest.cpp +++ b/llvm/unittests/tools/llvm-exegesis/Mips/TargetTest.cpp @@ -44,9 +44,22 @@ Matcher<MCInst> OpcodeIs(unsigned Opcode) { return Property(&MCInst::getOpcode, Eq(Opcode)); } -Matcher<MCInst> IsLoadLowImm(int64_t Reg, int64_t Value) { - return AllOf(OpcodeIs(Mips::ORi), - ElementsAre(IsReg(Reg), IsReg(Mips::ZERO), IsImm(Value))); +Matcher<MCInst> IsLoadLow16BitImm(unsigned Reg, int64_t Value, bool IsGPR32) { + const unsigned ZeroReg = IsGPR32 ? Mips::ZERO : Mips::ZERO_64; + const unsigned ORi = IsGPR32 ? Mips::ORi : Mips::ORi64; + return AllOf(OpcodeIs(ORi), + ElementsAre(IsReg(Reg), IsReg(ZeroReg), IsImm(Value))); +} + +Matcher<MCInst> IsLoadHigh16BitImm(unsigned Reg, int64_t Value, bool IsGPR32) { + const unsigned LUi = IsGPR32 ? Mips::LUi : Mips::LUi64; + return AllOf(OpcodeIs(LUi), ElementsAre(IsReg(Reg), IsImm(Value))); +} + +Matcher<MCInst> IsShift(unsigned Reg, uint16_t Amount, bool IsGPR32) { + const unsigned SLL = IsGPR32 ? Mips::SLL : Mips::SLL64_64; + return AllOf(OpcodeIs(SLL), + ElementsAre(IsReg(Reg), IsReg(Reg), IsImm(Amount))); } constexpr const char kTriple[] = "mips-unknown-linux"; @@ -70,11 +83,53 @@ protected: LLVMState State; }; -TEST_F(MipsTargetTest, SetRegToConstant) { +TEST_F(MipsTargetTest, SetGPR32RegTo16BitValue) { const uint16_t Value = 0xFFFFU; const unsigned Reg = Mips::T0; EXPECT_THAT(setRegTo(Reg, APInt(16, Value)), - ElementsAre(IsLoadLowImm(Reg, Value))); + ElementsAre(IsLoadLow16BitImm(Reg, Value, true))); +} + +TEST_F(MipsTargetTest, SetGPR64RegTo16BitValue) { + const uint16_t Value = 0xFFFFU; + const unsigned Reg = Mips::T0_64; + EXPECT_THAT(setRegTo(Reg, APInt(16, Value)), + ElementsAre(IsLoadLow16BitImm(Reg, Value, false))); +} + +TEST_F(MipsTargetTest, SetGPR32RegTo32BitValue) { + const uint32_t Value0 = 0xFFFF0000UL; + const unsigned Reg0 = Mips::T0; + EXPECT_THAT(setRegTo(Reg0, APInt(32, Value0)), + ElementsAre(IsLoadHigh16BitImm(Reg0, 0xFFFFU, true))); + const uint32_t Value1 = 0xFFFFFFFFUL; + const unsigned Reg1 = Mips::T1; + EXPECT_THAT(setRegTo(Reg1, APInt(32, Value1)), + ElementsAre(IsLoadHigh16BitImm(Reg1, 0xFFFFU, true), + IsLoadLow16BitImm(Reg1, 0xFFFFU, true))); +} + +TEST_F(MipsTargetTest, SetGPR64RegTo32BitValue) { + const uint32_t Value0 = 0x7FFF0000UL; + const unsigned Reg0 = Mips::T0_64; + EXPECT_THAT(setRegTo(Reg0, APInt(32, Value0)), + ElementsAre(IsLoadHigh16BitImm(Reg0, 0x7FFFU, false))); + const uint32_t Value1 = 0x7FFFFFFFUL; + const unsigned Reg1 = Mips::T1_64; + EXPECT_THAT(setRegTo(Reg1, APInt(32, Value1)), + ElementsAre(IsLoadHigh16BitImm(Reg1, 0x7FFFU, false), + IsLoadLow16BitImm(Reg1, 0xFFFFU, false))); + const uint32_t Value2 = 0xFFFF0000UL; + const unsigned Reg2 = Mips::T2_64; + EXPECT_THAT(setRegTo(Reg2, APInt(32, Value2)), + ElementsAre(IsLoadLow16BitImm(Reg2, 0xFFFFU, false), + IsShift(Reg2, 16, false))); + const uint32_t Value3 = 0xFFFFFFFFUL; + const unsigned Reg3 = Mips::T3_64; + EXPECT_THAT(setRegTo(Reg3, APInt(32, Value3)), + ElementsAre(IsLoadLow16BitImm(Reg3, 0xFFFFU, false), + IsShift(Reg3, 16, false), + IsLoadLow16BitImm(Reg3, 0xFFFFU, false))); } TEST_F(MipsTargetTest, DefaultPfmCounters) { |
