diff options
Diffstat (limited to 'llvm/tools')
| -rw-r--r-- | llvm/tools/llvm-mca/Backend.h | 6 | ||||
| -rw-r--r-- | llvm/tools/llvm-mca/Dispatch.h | 11 | ||||
| -rw-r--r-- | llvm/tools/llvm-mca/llvm-mca.cpp | 9 |
3 files changed, 10 insertions, 16 deletions
diff --git a/llvm/tools/llvm-mca/Backend.h b/llvm/tools/llvm-mca/Backend.h index 3f4fda73143..12e80777c77 100644 --- a/llvm/tools/llvm-mca/Backend.h +++ b/llvm/tools/llvm-mca/Backend.h @@ -62,15 +62,15 @@ public: Backend(const llvm::MCSubtargetInfo &Subtarget, const llvm::MCRegisterInfo &MRI, InstrBuilder &B, SourceMgr &Source, unsigned DispatchWidth = 0, unsigned RegisterFileSize = 0, - unsigned MaxRetirePerCycle = 0, unsigned LoadQueueSize = 0, - unsigned StoreQueueSize = 0, bool AssumeNoAlias = false) + unsigned LoadQueueSize = 0, unsigned StoreQueueSize = 0, + bool AssumeNoAlias = false) : STI(Subtarget), IB(B), HWS(llvm::make_unique<Scheduler>(this, Subtarget.getSchedModel(), LoadQueueSize, StoreQueueSize, AssumeNoAlias)), DU(llvm::make_unique<DispatchUnit>( this, STI, MRI, Subtarget.getSchedModel().MicroOpBufferSize, - RegisterFileSize, MaxRetirePerCycle, DispatchWidth, HWS.get())), + RegisterFileSize, DispatchWidth, HWS.get())), SM(Source), Cycles(0) { HWS->setDispatchUnit(DU.get()); } diff --git a/llvm/tools/llvm-mca/Dispatch.h b/llvm/tools/llvm-mca/Dispatch.h index c5a07418592..979e2a370dd 100644 --- a/llvm/tools/llvm-mca/Dispatch.h +++ b/llvm/tools/llvm-mca/Dispatch.h @@ -192,9 +192,9 @@ private: DispatchUnit *Owner; public: - RetireControlUnit(unsigned NumSlots, unsigned RPC, DispatchUnit *DU) + RetireControlUnit(unsigned NumSlots, DispatchUnit *DU) : NextAvailableSlotIdx(0), CurrentInstructionSlotIdx(0), - AvailableSlots(NumSlots), MaxRetirePerCycle(RPC), Owner(DU) { + AvailableSlots(NumSlots), MaxRetirePerCycle(0), Owner(DU) { assert(NumSlots && "Expected at least one slot!"); Queue.resize(NumSlots); } @@ -266,14 +266,13 @@ class DispatchUnit { public: DispatchUnit(Backend *B, const llvm::MCSubtargetInfo &STI, const llvm::MCRegisterInfo &MRI, unsigned MicroOpBufferSize, - unsigned RegisterFileSize, unsigned MaxRetirePerCycle, - unsigned MaxDispatchWidth, Scheduler *Sched) + unsigned RegisterFileSize, unsigned MaxDispatchWidth, + Scheduler *Sched) : DispatchWidth(MaxDispatchWidth), AvailableEntries(MaxDispatchWidth), CarryOver(0U), SC(Sched), RAT(llvm::make_unique<RegisterFile>(STI.getSchedModel(), MRI, RegisterFileSize)), - RCU(llvm::make_unique<RetireControlUnit>(MicroOpBufferSize, - MaxRetirePerCycle, this)), + RCU(llvm::make_unique<RetireControlUnit>(MicroOpBufferSize, this)), Owner(B) {} unsigned getDispatchWidth() const { return DispatchWidth; } diff --git a/llvm/tools/llvm-mca/llvm-mca.cpp b/llvm/tools/llvm-mca/llvm-mca.cpp index 7ad31df3ce8..efd0d1957fd 100644 --- a/llvm/tools/llvm-mca/llvm-mca.cpp +++ b/llvm/tools/llvm-mca/llvm-mca.cpp @@ -81,11 +81,6 @@ static cl::opt<unsigned> DispatchWidth( cl::desc("Dispatch Width. By default it is set equal to IssueWidth"), cl::init(0)); -static cl::opt<unsigned> MaxRetirePerCycle( - "max-retire-per-cycle", - cl::desc("Maximum number of instructions that can be retired in one cycle"), - cl::init(0)); - static cl::opt<unsigned> RegisterFileSize("register-file-size", cl::desc("Maximum number of temporary registers which can " @@ -361,8 +356,8 @@ int main(int argc, char **argv) { } std::unique_ptr<mca::Backend> B = llvm::make_unique<mca::Backend>( - *STI, *MRI, *IB, *S, Width, RegisterFileSize, MaxRetirePerCycle, - LoadQueueSize, StoreQueueSize, AssumeNoAlias); + *STI, *MRI, *IB, *S, Width, RegisterFileSize, LoadQueueSize, + StoreQueueSize, AssumeNoAlias); std::unique_ptr<mca::BackendPrinter> Printer = llvm::make_unique<mca::BackendPrinter>(*B); |
