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-rw-r--r--llvm/tools/llvm-mca/Backend.cpp8
-rw-r--r--llvm/tools/llvm-mca/Dispatch.cpp13
-rw-r--r--llvm/tools/llvm-mca/InstrBuilder.cpp22
-rw-r--r--llvm/tools/llvm-mca/LSUnit.cpp16
-rw-r--r--llvm/tools/llvm-mca/Scheduler.cpp19
5 files changed, 41 insertions, 37 deletions
diff --git a/llvm/tools/llvm-mca/Backend.cpp b/llvm/tools/llvm-mca/Backend.cpp
index de345108fae..4e6ec482eef 100644
--- a/llvm/tools/llvm-mca/Backend.cpp
+++ b/llvm/tools/llvm-mca/Backend.cpp
@@ -48,7 +48,7 @@ void Backend::runCycle(unsigned Cycle) {
}
void Backend::notifyCycleBegin(unsigned Cycle) {
- DEBUG(dbgs() << "[E] Cycle begin: " << Cycle << '\n');
+ LLVM_DEBUG(dbgs() << "[E] Cycle begin: " << Cycle << '\n');
for (HWEventListener *Listener : Listeners)
Listener->onCycleBegin();
@@ -67,8 +67,8 @@ void Backend::notifyStallEvent(const HWStallEvent &Event) {
}
void Backend::notifyResourceAvailable(const ResourceRef &RR) {
- DEBUG(dbgs() << "[E] Resource Available: [" << RR.first << '.' << RR.second
- << "]\n");
+ LLVM_DEBUG(dbgs() << "[E] Resource Available: [" << RR.first << '.'
+ << RR.second << "]\n");
for (HWEventListener *Listener : Listeners)
Listener->onResourceAvailable(RR);
}
@@ -84,7 +84,7 @@ void Backend::notifyReleasedBuffers(ArrayRef<unsigned> Buffers) {
}
void Backend::notifyCycleEnd(unsigned Cycle) {
- DEBUG(dbgs() << "[E] Cycle end: " << Cycle << "\n\n");
+ LLVM_DEBUG(dbgs() << "[E] Cycle end: " << Cycle << "\n\n");
for (HWEventListener *Listener : Listeners)
Listener->onCycleEnd();
}
diff --git a/llvm/tools/llvm-mca/Dispatch.cpp b/llvm/tools/llvm-mca/Dispatch.cpp
index b077f0af21d..2c0227d33a9 100644
--- a/llvm/tools/llvm-mca/Dispatch.cpp
+++ b/llvm/tools/llvm-mca/Dispatch.cpp
@@ -176,7 +176,7 @@ void RegisterFile::collectWrites(SmallVectorImpl<WriteState *> &Writes,
assert(RegID && RegID < RegisterMappings.size());
WriteState *WS = RegisterMappings[RegID].first;
if (WS) {
- DEBUG(dbgs() << "Found a dependent use of RegID=" << RegID << '\n');
+ LLVM_DEBUG(dbgs() << "Found a dependent use of RegID=" << RegID << '\n');
Writes.push_back(WS);
}
@@ -184,8 +184,8 @@ void RegisterFile::collectWrites(SmallVectorImpl<WriteState *> &Writes,
for (MCSubRegIterator I(RegID, &MRI); I.isValid(); ++I) {
WS = RegisterMappings[*I].first;
if (WS && std::find(Writes.begin(), Writes.end(), WS) == Writes.end()) {
- DEBUG(dbgs() << "Found a dependent use of subReg " << *I << " (part of "
- << RegID << ")\n");
+ LLVM_DEBUG(dbgs() << "Found a dependent use of subReg " << *I
+ << " (part of " << RegID << ")\n");
Writes.push_back(WS);
}
}
@@ -254,12 +254,12 @@ void RegisterFile::dump() const {
void DispatchUnit::notifyInstructionDispatched(const InstRef &IR,
ArrayRef<unsigned> UsedRegs) {
- DEBUG(dbgs() << "[E] Instruction Dispatched: " << IR << '\n');
+ LLVM_DEBUG(dbgs() << "[E] Instruction Dispatched: " << IR << '\n');
Owner->notifyInstructionEvent(HWInstructionDispatchedEvent(IR, UsedRegs));
}
void DispatchUnit::notifyInstructionRetired(const InstRef &IR) {
- DEBUG(dbgs() << "[E] Instruction Retired: " << IR << '\n');
+ LLVM_DEBUG(dbgs() << "[E] Instruction Retired: " << IR << '\n');
SmallVector<unsigned, 4> FreedRegs(RAT->getNumRegisterFiles());
for (const std::unique_ptr<WriteState> &WS : IR.getInstruction()->getDefs())
RAT->invalidateRegisterMapping(*WS.get(), FreedRegs);
@@ -302,7 +302,8 @@ void DispatchUnit::updateRAWDependencies(ReadState &RS,
collectWrites(DependentWrites, RS.getRegisterID());
RS.setDependentWrites(DependentWrites.size());
- DEBUG(dbgs() << "Found " << DependentWrites.size() << " dependent writes\n");
+ LLVM_DEBUG(dbgs() << "Found " << DependentWrites.size()
+ << " dependent writes\n");
// We know that this read depends on all the writes in DependentWrites.
// For each write, check if we have ReadAdvance information, and use it
// to figure out in how many cycles this read becomes available.
diff --git a/llvm/tools/llvm-mca/InstrBuilder.cpp b/llvm/tools/llvm-mca/InstrBuilder.cpp
index 7b4ad38d865..bca3e4bc0d7 100644
--- a/llvm/tools/llvm-mca/InstrBuilder.cpp
+++ b/llvm/tools/llvm-mca/InstrBuilder.cpp
@@ -113,7 +113,7 @@ static void initializeUsedResources(InstrDesc &ID,
}
}
- DEBUG({
+ LLVM_DEBUG({
for (const std::pair<uint64_t, ResourceUsage> &R : ID.Resources)
dbgs() << "\t\tMask=" << R.first << ", cy=" << R.second.size() << '\n';
for (const uint64_t R : ID.Buffers)
@@ -259,7 +259,7 @@ static void populateWrites(InstrDesc &ID, const MCInst &MCI,
}
Write.FullyUpdatesSuperRegs = FullyUpdatesSuperRegisters;
Write.IsOptionalDef = false;
- DEBUG({
+ LLVM_DEBUG({
dbgs() << "\t\tOpIdx=" << Write.OpIndex << ", Latency=" << Write.Latency
<< ", WriteResourceID=" << Write.SClassOrWriteResourceID << '\n';
});
@@ -290,10 +290,10 @@ static void populateWrites(InstrDesc &ID, const MCInst &MCI,
Write.IsOptionalDef = false;
assert(Write.RegisterID != 0 && "Expected a valid phys register!");
- DEBUG(dbgs() << "\t\tOpIdx=" << Write.OpIndex << ", PhysReg="
- << Write.RegisterID << ", Latency=" << Write.Latency
- << ", WriteResourceID=" << Write.SClassOrWriteResourceID
- << '\n');
+ LLVM_DEBUG(dbgs() << "\t\tOpIdx=" << Write.OpIndex << ", PhysReg="
+ << Write.RegisterID << ", Latency=" << Write.Latency
+ << ", WriteResourceID=" << Write.SClassOrWriteResourceID
+ << '\n');
}
if (MCDesc.hasOptionalDef()) {
@@ -352,7 +352,7 @@ static void populateReads(InstrDesc &ID, const MCInst &MCI,
Read.UseIndex = CurrentUse;
Read.HasReadAdvanceEntries = HasReadAdvanceEntries;
Read.SchedClassID = SchedClassID;
- DEBUG(dbgs() << "\t\tOpIdx=" << Read.OpIndex);
+ LLVM_DEBUG(dbgs() << "\t\tOpIdx=" << Read.OpIndex);
}
for (unsigned CurrentUse = 0; CurrentUse < NumImplicitUses; ++CurrentUse) {
@@ -362,8 +362,8 @@ static void populateReads(InstrDesc &ID, const MCInst &MCI,
Read.RegisterID = MCDesc.getImplicitUses()[CurrentUse];
Read.HasReadAdvanceEntries = HasReadAdvanceEntries;
Read.SchedClassID = SchedClassID;
- DEBUG(dbgs() << "\t\tOpIdx=" << Read.OpIndex
- << ", RegisterID=" << Read.RegisterID << '\n');
+ LLVM_DEBUG(dbgs() << "\t\tOpIdx=" << Read.OpIndex
+ << ", RegisterID=" << Read.RegisterID << '\n');
}
}
@@ -413,8 +413,8 @@ const InstrDesc &InstrBuilder::createInstrDescImpl(const MCInst &MCI) {
populateWrites(*ID, MCI, MCDesc, SCDesc, STI);
populateReads(*ID, MCI, MCDesc, SCDesc, STI);
- DEBUG(dbgs() << "\t\tMaxLatency=" << ID->MaxLatency << '\n');
- DEBUG(dbgs() << "\t\tNumMicroOps=" << ID->NumMicroOps << '\n');
+ LLVM_DEBUG(dbgs() << "\t\tMaxLatency=" << ID->MaxLatency << '\n');
+ LLVM_DEBUG(dbgs() << "\t\tNumMicroOps=" << ID->NumMicroOps << '\n');
// Now add the new descriptor.
Descriptors[Opcode] = std::move(ID);
diff --git a/llvm/tools/llvm-mca/LSUnit.cpp b/llvm/tools/llvm-mca/LSUnit.cpp
index 1b6d8485cfe..dfd3e53fb49 100644
--- a/llvm/tools/llvm-mca/LSUnit.cpp
+++ b/llvm/tools/llvm-mca/LSUnit.cpp
@@ -36,8 +36,8 @@ void LSUnit::assignLQSlot(unsigned Index) {
assert(!isLQFull());
assert(LoadQueue.count(Index) == 0);
- DEBUG(dbgs() << "[LSUnit] - AssignLQSlot <Idx=" << Index
- << ",slot=" << LoadQueue.size() << ">\n");
+ LLVM_DEBUG(dbgs() << "[LSUnit] - AssignLQSlot <Idx=" << Index
+ << ",slot=" << LoadQueue.size() << ">\n");
LoadQueue.insert(Index);
}
@@ -45,8 +45,8 @@ void LSUnit::assignSQSlot(unsigned Index) {
assert(!isSQFull());
assert(StoreQueue.count(Index) == 0);
- DEBUG(dbgs() << "[LSUnit] - AssignSQSlot <Idx=" << Index
- << ",slot=" << StoreQueue.size() << ">\n");
+ LLVM_DEBUG(dbgs() << "[LSUnit] - AssignSQSlot <Idx=" << Index
+ << ",slot=" << StoreQueue.size() << ">\n");
StoreQueue.insert(Index);
}
@@ -123,15 +123,15 @@ void LSUnit::onInstructionExecuted(const InstRef &IR) {
const unsigned Index = IR.getSourceIndex();
std::set<unsigned>::iterator it = LoadQueue.find(Index);
if (it != LoadQueue.end()) {
- DEBUG(dbgs() << "[LSUnit]: Instruction idx=" << Index
- << " has been removed from the load queue.\n");
+ LLVM_DEBUG(dbgs() << "[LSUnit]: Instruction idx=" << Index
+ << " has been removed from the load queue.\n");
LoadQueue.erase(it);
}
it = StoreQueue.find(Index);
if (it != StoreQueue.end()) {
- DEBUG(dbgs() << "[LSUnit]: Instruction idx=" << Index
- << " has been removed from the store queue.\n");
+ LLVM_DEBUG(dbgs() << "[LSUnit]: Instruction idx=" << Index
+ << " has been removed from the store queue.\n");
StoreQueue.erase(it);
}
diff --git a/llvm/tools/llvm-mca/Scheduler.cpp b/llvm/tools/llvm-mca/Scheduler.cpp
index 5df677d741b..4abdc97bb0e 100644
--- a/llvm/tools/llvm-mca/Scheduler.cpp
+++ b/llvm/tools/llvm-mca/Scheduler.cpp
@@ -245,7 +245,8 @@ void Scheduler::scheduleInstruction(InstRef &IR) {
// If necessary, reserve queue entries in the load-store unit (LSU).
bool Reserved = LSU->reserve(IR);
if (!IR.getInstruction()->isReady() || (Reserved && !LSU->isReady(IR))) {
- DEBUG(dbgs() << "[SCHEDULER] Adding " << Idx << " to the Wait Queue\n");
+ LLVM_DEBUG(dbgs() << "[SCHEDULER] Adding " << Idx
+ << " to the Wait Queue\n");
WaitQueue[Idx] = IR.getInstruction();
return;
}
@@ -266,12 +267,14 @@ void Scheduler::scheduleInstruction(InstRef &IR) {
// resources (i.e. BufferSize=1) is consumed.
if (!IsZeroLatency && !Resources->mustIssueImmediately(Desc)) {
- DEBUG(dbgs() << "[SCHEDULER] Adding " << IR << " to the Ready Queue\n");
+ LLVM_DEBUG(dbgs() << "[SCHEDULER] Adding " << IR
+ << " to the Ready Queue\n");
ReadyQueue[IR.getSourceIndex()] = IR.getInstruction();
return;
}
- DEBUG(dbgs() << "[SCHEDULER] Instruction " << IR << " issued immediately\n");
+ LLVM_DEBUG(dbgs() << "[SCHEDULER] Instruction " << IR
+ << " issued immediately\n");
// Release buffered resources and issue MCIS to the underlying pipelines.
issueInstruction(IR);
}
@@ -441,8 +444,8 @@ void Scheduler::updateIssuedQueue(SmallVectorImpl<InstRef> &Executed) {
++I;
IssuedQueue.erase(ToRemove);
} else {
- DEBUG(dbgs() << "[SCHEDULER]: Instruction " << Entry.first
- << " is still executing.\n");
+ LLVM_DEBUG(dbgs() << "[SCHEDULER]: Instruction " << Entry.first
+ << " is still executing.\n");
++I;
}
}
@@ -450,7 +453,7 @@ void Scheduler::updateIssuedQueue(SmallVectorImpl<InstRef> &Executed) {
void Scheduler::notifyInstructionIssued(
const InstRef &IR, ArrayRef<std::pair<ResourceRef, double>> Used) {
- DEBUG({
+ LLVM_DEBUG({
dbgs() << "[E] Instruction Issued: " << IR << '\n';
for (const std::pair<ResourceRef, unsigned> &Resource : Used) {
dbgs() << "[E] Resource Used: [" << Resource.first.first << '.'
@@ -463,14 +466,14 @@ void Scheduler::notifyInstructionIssued(
void Scheduler::notifyInstructionExecuted(const InstRef &IR) {
LSU->onInstructionExecuted(IR);
- DEBUG(dbgs() << "[E] Instruction Executed: " << IR << '\n');
+ LLVM_DEBUG(dbgs() << "[E] Instruction Executed: " << IR << '\n');
Owner->notifyInstructionEvent(
HWInstructionEvent(HWInstructionEvent::Executed, IR));
DU->onInstructionExecuted(IR.getInstruction()->getRCUTokenID());
}
void Scheduler::notifyInstructionReady(const InstRef &IR) {
- DEBUG(dbgs() << "[E] Instruction Ready: " << IR << '\n');
+ LLVM_DEBUG(dbgs() << "[E] Instruction Ready: " << IR << '\n');
Owner->notifyInstructionEvent(
HWInstructionEvent(HWInstructionEvent::Ready, IR));
}
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