diff options
Diffstat (limited to 'llvm/tools/llvm-exegesis/lib/X86')
| -rw-r--r-- | llvm/tools/llvm-exegesis/lib/X86/Target.cpp | 303 |
1 files changed, 147 insertions, 156 deletions
diff --git a/llvm/tools/llvm-exegesis/lib/X86/Target.cpp b/llvm/tools/llvm-exegesis/lib/X86/Target.cpp index dd07af45b42..6cf3d465dd9 100644 --- a/llvm/tools/llvm-exegesis/lib/X86/Target.cpp +++ b/llvm/tools/llvm-exegesis/lib/X86/Target.cpp @@ -148,34 +148,31 @@ static Error isInvalidMemoryInstr(const Instruction &Instr) { } } -static llvm::Error IsInvalidOpcode(const Instruction &Instr) { +static Error IsInvalidOpcode(const Instruction &Instr) { const auto OpcodeName = Instr.Name; if ((Instr.Description->TSFlags & X86II::FormMask) == X86II::Pseudo) - return llvm::make_error<Failure>("unsupported opcode: pseudo instruction"); + return make_error<Failure>("unsupported opcode: pseudo instruction"); if (OpcodeName.startswith("POPF") || OpcodeName.startswith("PUSHF") || OpcodeName.startswith("ADJCALLSTACK")) - return llvm::make_error<Failure>( - "unsupported opcode: Push/Pop/AdjCallStack"); - if (llvm::Error Error = isInvalidMemoryInstr(Instr)) + return make_error<Failure>("unsupported opcode: Push/Pop/AdjCallStack"); + if (Error Error = isInvalidMemoryInstr(Instr)) return Error; // We do not handle instructions with OPERAND_PCREL. for (const Operand &Op : Instr.Operands) if (Op.isExplicit() && - Op.getExplicitOperandInfo().OperandType == llvm::MCOI::OPERAND_PCREL) - return llvm::make_error<Failure>( - "unsupported opcode: PC relative operand"); + Op.getExplicitOperandInfo().OperandType == MCOI::OPERAND_PCREL) + return make_error<Failure>("unsupported opcode: PC relative operand"); // We do not handle second-form X87 instructions. We only handle first-form // ones (_Fp), see comment in X86InstrFPStack.td. for (const Operand &Op : Instr.Operands) if (Op.isReg() && Op.isExplicit() && - Op.getExplicitOperandInfo().RegClass == llvm::X86::RSTRegClassID) - return llvm::make_error<Failure>( - "unsupported second-form X87 instruction"); - return llvm::Error::success(); + Op.getExplicitOperandInfo().RegClass == X86::RSTRegClassID) + return make_error<Failure>("unsupported second-form X87 instruction"); + return Error::success(); } static unsigned getX86FPFlags(const Instruction &Instr) { - return Instr.Description->TSFlags & llvm::X86II::FPTypeMask; + return Instr.Description->TSFlags & X86II::FPTypeMask; } // Helper to fill a memory operand with a value. @@ -188,7 +185,7 @@ static void setMemOp(InstructionTemplate &IT, int OpIdx, // Common (latency, uops) code for LEA templates. `GetDestReg` takes the // addressing base and index registers and returns the LEA destination register. -static llvm::Expected<std::vector<CodeTemplate>> generateLEATemplatesCommon( +static Expected<std::vector<CodeTemplate>> generateLEATemplatesCommon( const Instruction &Instr, const BitVector &ForbiddenRegisters, const LLVMState &State, const SnippetGenerator::Options &Opts, std::function<unsigned(unsigned, unsigned)> GetDestReg) { @@ -249,13 +246,13 @@ class X86LatencySnippetGenerator : public LatencySnippetGenerator { public: using LatencySnippetGenerator::LatencySnippetGenerator; - llvm::Expected<std::vector<CodeTemplate>> + Expected<std::vector<CodeTemplate>> generateCodeTemplates(const Instruction &Instr, const BitVector &ForbiddenRegisters) const override; }; } // namespace -llvm::Expected<std::vector<CodeTemplate>> +Expected<std::vector<CodeTemplate>> X86LatencySnippetGenerator::generateCodeTemplates( const Instruction &Instr, const BitVector &ForbiddenRegisters) const { if (auto E = IsInvalidOpcode(Instr)) @@ -273,17 +270,17 @@ X86LatencySnippetGenerator::generateCodeTemplates( } switch (getX86FPFlags(Instr)) { - case llvm::X86II::NotFP: + case X86II::NotFP: return LatencySnippetGenerator::generateCodeTemplates(Instr, ForbiddenRegisters); - case llvm::X86II::ZeroArgFP: - case llvm::X86II::OneArgFP: - case llvm::X86II::SpecialFP: - case llvm::X86II::CompareFP: - case llvm::X86II::CondMovFP: - return llvm::make_error<Failure>("Unsupported x87 Instruction"); - case llvm::X86II::OneArgFPRW: - case llvm::X86II::TwoArgFP: + case X86II::ZeroArgFP: + case X86II::OneArgFP: + case X86II::SpecialFP: + case X86II::CompareFP: + case X86II::CondMovFP: + return make_error<Failure>("Unsupported x87 Instruction"); + case X86II::OneArgFPRW: + case X86II::TwoArgFP: // These are instructions like // - `ST(0) = fsqrt(ST(0))` (OneArgFPRW) // - `ST(0) = ST(0) + ST(i)` (TwoArgFP) @@ -299,14 +296,14 @@ class X86UopsSnippetGenerator : public UopsSnippetGenerator { public: using UopsSnippetGenerator::UopsSnippetGenerator; - llvm::Expected<std::vector<CodeTemplate>> + Expected<std::vector<CodeTemplate>> generateCodeTemplates(const Instruction &Instr, const BitVector &ForbiddenRegisters) const override; }; } // namespace -llvm::Expected<std::vector<CodeTemplate>> +Expected<std::vector<CodeTemplate>> X86UopsSnippetGenerator::generateCodeTemplates( const Instruction &Instr, const BitVector &ForbiddenRegisters) const { if (auto E = IsInvalidOpcode(Instr)) @@ -335,23 +332,23 @@ X86UopsSnippetGenerator::generateCodeTemplates( } switch (getX86FPFlags(Instr)) { - case llvm::X86II::NotFP: + case X86II::NotFP: return UopsSnippetGenerator::generateCodeTemplates(Instr, ForbiddenRegisters); - case llvm::X86II::ZeroArgFP: - case llvm::X86II::OneArgFP: - case llvm::X86II::SpecialFP: - return llvm::make_error<Failure>("Unsupported x87 Instruction"); - case llvm::X86II::OneArgFPRW: - case llvm::X86II::TwoArgFP: + case X86II::ZeroArgFP: + case X86II::OneArgFP: + case X86II::SpecialFP: + return make_error<Failure>("Unsupported x87 Instruction"); + case X86II::OneArgFPRW: + case X86II::TwoArgFP: // These are instructions like // - `ST(0) = fsqrt(ST(0))` (OneArgFPRW) // - `ST(0) = ST(0) + ST(i)` (TwoArgFP) // They are intrinsically serial and do not modify the state of the stack. // We generate the same code for latency and uops. return generateSelfAliasingCodeTemplates(Instr); - case llvm::X86II::CompareFP: - case llvm::X86II::CondMovFP: + case X86II::CompareFP: + case X86II::CondMovFP: // We can compute uops for any FP instruction that does not grow or shrink // the stack (either do not touch the stack or push as much as they pop). return generateUnconstrainedCodeTemplates( @@ -364,66 +361,66 @@ X86UopsSnippetGenerator::generateCodeTemplates( static unsigned getLoadImmediateOpcode(unsigned RegBitWidth) { switch (RegBitWidth) { case 8: - return llvm::X86::MOV8ri; + return X86::MOV8ri; case 16: - return llvm::X86::MOV16ri; + return X86::MOV16ri; case 32: - return llvm::X86::MOV32ri; + return X86::MOV32ri; case 64: - return llvm::X86::MOV64ri; + return X86::MOV64ri; } llvm_unreachable("Invalid Value Width"); } // Generates instruction to load an immediate value into a register. -static llvm::MCInst loadImmediate(unsigned Reg, unsigned RegBitWidth, - const llvm::APInt &Value) { +static MCInst loadImmediate(unsigned Reg, unsigned RegBitWidth, + const APInt &Value) { if (Value.getBitWidth() > RegBitWidth) llvm_unreachable("Value must fit in the Register"); - return llvm::MCInstBuilder(getLoadImmediateOpcode(RegBitWidth)) + return MCInstBuilder(getLoadImmediateOpcode(RegBitWidth)) .addReg(Reg) .addImm(Value.getZExtValue()); } // Allocates scratch memory on the stack. -static llvm::MCInst allocateStackSpace(unsigned Bytes) { - return llvm::MCInstBuilder(llvm::X86::SUB64ri8) - .addReg(llvm::X86::RSP) - .addReg(llvm::X86::RSP) +static MCInst allocateStackSpace(unsigned Bytes) { + return MCInstBuilder(X86::SUB64ri8) + .addReg(X86::RSP) + .addReg(X86::RSP) .addImm(Bytes); } // Fills scratch memory at offset `OffsetBytes` with value `Imm`. -static llvm::MCInst fillStackSpace(unsigned MovOpcode, unsigned OffsetBytes, - uint64_t Imm) { - return llvm::MCInstBuilder(MovOpcode) +static MCInst fillStackSpace(unsigned MovOpcode, unsigned OffsetBytes, + uint64_t Imm) { + return MCInstBuilder(MovOpcode) // Address = ESP - .addReg(llvm::X86::RSP) // BaseReg - .addImm(1) // ScaleAmt - .addReg(0) // IndexReg - .addImm(OffsetBytes) // Disp - .addReg(0) // Segment + .addReg(X86::RSP) // BaseReg + .addImm(1) // ScaleAmt + .addReg(0) // IndexReg + .addImm(OffsetBytes) // Disp + .addReg(0) // Segment // Immediate. .addImm(Imm); } // Loads scratch memory into register `Reg` using opcode `RMOpcode`. -static llvm::MCInst loadToReg(unsigned Reg, unsigned RMOpcode) { - return llvm::MCInstBuilder(RMOpcode) +static MCInst loadToReg(unsigned Reg, unsigned RMOpcode) { + return MCInstBuilder(RMOpcode) .addReg(Reg) // Address = ESP - .addReg(llvm::X86::RSP) // BaseReg - .addImm(1) // ScaleAmt - .addReg(0) // IndexReg - .addImm(0) // Disp - .addReg(0); // Segment + .addReg(X86::RSP) // BaseReg + .addImm(1) // ScaleAmt + .addReg(0) // IndexReg + .addImm(0) // Disp + .addReg(0); // Segment } // Releases scratch memory. -static llvm::MCInst releaseStackSpace(unsigned Bytes) { - return llvm::MCInstBuilder(llvm::X86::ADD64ri8) - .addReg(llvm::X86::RSP) - .addReg(llvm::X86::RSP) +static MCInst releaseStackSpace(unsigned Bytes) { + return MCInstBuilder(X86::ADD64ri8) + .addReg(X86::RSP) + .addReg(X86::RSP) .addImm(Bytes); } @@ -431,19 +428,19 @@ static llvm::MCInst releaseStackSpace(unsigned Bytes) { // constant and provide methods to load the stack value into a register. namespace { struct ConstantInliner { - explicit ConstantInliner(const llvm::APInt &Constant) : Constant_(Constant) {} + explicit ConstantInliner(const APInt &Constant) : Constant_(Constant) {} - std::vector<llvm::MCInst> loadAndFinalize(unsigned Reg, unsigned RegBitWidth, - unsigned Opcode); + std::vector<MCInst> loadAndFinalize(unsigned Reg, unsigned RegBitWidth, + unsigned Opcode); - std::vector<llvm::MCInst> loadX87STAndFinalize(unsigned Reg); + std::vector<MCInst> loadX87STAndFinalize(unsigned Reg); - std::vector<llvm::MCInst> loadX87FPAndFinalize(unsigned Reg); + std::vector<MCInst> loadX87FPAndFinalize(unsigned Reg); - std::vector<llvm::MCInst> popFlagAndFinalize(); + std::vector<MCInst> popFlagAndFinalize(); private: - ConstantInliner &add(const llvm::MCInst &Inst) { + ConstantInliner &add(const MCInst &Inst) { Instructions.push_back(Inst); return *this; } @@ -452,14 +449,14 @@ private: static constexpr const unsigned kF80Bytes = 10; // 80 bits. - llvm::APInt Constant_; - std::vector<llvm::MCInst> Instructions; + APInt Constant_; + std::vector<MCInst> Instructions; }; } // namespace -std::vector<llvm::MCInst> ConstantInliner::loadAndFinalize(unsigned Reg, - unsigned RegBitWidth, - unsigned Opcode) { +std::vector<MCInst> ConstantInliner::loadAndFinalize(unsigned Reg, + unsigned RegBitWidth, + unsigned Opcode) { assert((RegBitWidth & 7) == 0 && "RegBitWidth must be a multiple of 8 bits"); initStack(RegBitWidth / 8); add(loadToReg(Reg, Opcode)); @@ -467,62 +464,62 @@ std::vector<llvm::MCInst> ConstantInliner::loadAndFinalize(unsigned Reg, return std::move(Instructions); } -std::vector<llvm::MCInst> ConstantInliner::loadX87STAndFinalize(unsigned Reg) { +std::vector<MCInst> ConstantInliner::loadX87STAndFinalize(unsigned Reg) { initStack(kF80Bytes); - add(llvm::MCInstBuilder(llvm::X86::LD_F80m) + add(MCInstBuilder(X86::LD_F80m) // Address = ESP - .addReg(llvm::X86::RSP) // BaseReg - .addImm(1) // ScaleAmt - .addReg(0) // IndexReg - .addImm(0) // Disp - .addReg(0)); // Segment - if (Reg != llvm::X86::ST0) - add(llvm::MCInstBuilder(llvm::X86::ST_Frr).addReg(Reg)); + .addReg(X86::RSP) // BaseReg + .addImm(1) // ScaleAmt + .addReg(0) // IndexReg + .addImm(0) // Disp + .addReg(0)); // Segment + if (Reg != X86::ST0) + add(MCInstBuilder(X86::ST_Frr).addReg(Reg)); add(releaseStackSpace(kF80Bytes)); return std::move(Instructions); } -std::vector<llvm::MCInst> ConstantInliner::loadX87FPAndFinalize(unsigned Reg) { +std::vector<MCInst> ConstantInliner::loadX87FPAndFinalize(unsigned Reg) { initStack(kF80Bytes); - add(llvm::MCInstBuilder(llvm::X86::LD_Fp80m) + add(MCInstBuilder(X86::LD_Fp80m) .addReg(Reg) // Address = ESP - .addReg(llvm::X86::RSP) // BaseReg - .addImm(1) // ScaleAmt - .addReg(0) // IndexReg - .addImm(0) // Disp - .addReg(0)); // Segment + .addReg(X86::RSP) // BaseReg + .addImm(1) // ScaleAmt + .addReg(0) // IndexReg + .addImm(0) // Disp + .addReg(0)); // Segment add(releaseStackSpace(kF80Bytes)); return std::move(Instructions); } -std::vector<llvm::MCInst> ConstantInliner::popFlagAndFinalize() { +std::vector<MCInst> ConstantInliner::popFlagAndFinalize() { initStack(8); - add(llvm::MCInstBuilder(llvm::X86::POPF64)); + add(MCInstBuilder(X86::POPF64)); return std::move(Instructions); } void ConstantInliner::initStack(unsigned Bytes) { assert(Constant_.getBitWidth() <= Bytes * 8 && "Value does not have the correct size"); - const llvm::APInt WideConstant = Constant_.getBitWidth() < Bytes * 8 - ? Constant_.sext(Bytes * 8) - : Constant_; + const APInt WideConstant = Constant_.getBitWidth() < Bytes * 8 + ? Constant_.sext(Bytes * 8) + : Constant_; add(allocateStackSpace(Bytes)); size_t ByteOffset = 0; for (; Bytes - ByteOffset >= 4; ByteOffset += 4) add(fillStackSpace( - llvm::X86::MOV32mi, ByteOffset, + X86::MOV32mi, ByteOffset, WideConstant.extractBits(32, ByteOffset * 8).getZExtValue())); if (Bytes - ByteOffset >= 2) { add(fillStackSpace( - llvm::X86::MOV16mi, ByteOffset, + X86::MOV16mi, ByteOffset, WideConstant.extractBits(16, ByteOffset * 8).getZExtValue())); ByteOffset += 2; } if (Bytes - ByteOffset >= 1) add(fillStackSpace( - llvm::X86::MOV8mi, ByteOffset, + X86::MOV8mi, ByteOffset, WideConstant.extractBits(8, ByteOffset * 8).getZExtValue())); } @@ -534,28 +531,27 @@ public: ExegesisX86Target() : ExegesisTarget(X86CpuPfmCounters) {} private: - void addTargetSpecificPasses(llvm::PassManagerBase &PM) const override; + void addTargetSpecificPasses(PassManagerBase &PM) const override; - unsigned getScratchMemoryRegister(const llvm::Triple &TT) const override; + unsigned getScratchMemoryRegister(const Triple &TT) const override; - unsigned getLoopCounterRegister(const llvm::Triple &) const override; + unsigned getLoopCounterRegister(const Triple &) const override; unsigned getMaxMemoryAccessSize() const override { return 64; } void randomizeMCOperand(const Instruction &Instr, const Variable &Var, - llvm::MCOperand &AssignedValue, - const llvm::BitVector &ForbiddenRegs) const override; + MCOperand &AssignedValue, + const BitVector &ForbiddenRegs) const override; void fillMemoryOperands(InstructionTemplate &IT, unsigned Reg, unsigned Offset) const override; void decrementLoopCounterAndJump(MachineBasicBlock &MBB, MachineBasicBlock &TargetMBB, - const llvm::MCInstrInfo &MII) const override; + const MCInstrInfo &MII) const override; - std::vector<llvm::MCInst> setRegTo(const llvm::MCSubtargetInfo &STI, - unsigned Reg, - const llvm::APInt &Value) const override; + std::vector<MCInst> setRegTo(const MCSubtargetInfo &STI, unsigned Reg, + const APInt &Value) const override; ArrayRef<unsigned> getUnavailableRegisters() const override { return makeArrayRef(kUnavailableRegisters, @@ -575,8 +571,8 @@ private: return std::make_unique<X86UopsSnippetGenerator>(State, Opts); } - bool matchesArch(llvm::Triple::ArchType Arch) const override { - return Arch == llvm::Triple::x86_64 || Arch == llvm::Triple::x86; + bool matchesArch(Triple::ArchType Arch) const override { + return Arch == Triple::x86_64 || Arch == Triple::x86; } static const unsigned kUnavailableRegisters[4]; @@ -594,24 +590,21 @@ constexpr const unsigned kLoopCounterReg = X86::R8; } // namespace -void ExegesisX86Target::addTargetSpecificPasses( - llvm::PassManagerBase &PM) const { +void ExegesisX86Target::addTargetSpecificPasses(PassManagerBase &PM) const { // Lowers FP pseudo-instructions, e.g. ABS_Fp32 -> ABS_F. - PM.add(llvm::createX86FloatingPointStackifierPass()); + PM.add(createX86FloatingPointStackifierPass()); } -unsigned -ExegesisX86Target::getScratchMemoryRegister(const llvm::Triple &TT) const { +unsigned ExegesisX86Target::getScratchMemoryRegister(const Triple &TT) const { if (!TT.isArch64Bit()) { // FIXME: This would require popping from the stack, so we would have to // add some additional setup code. return 0; } - return TT.isOSWindows() ? llvm::X86::RCX : llvm::X86::RDI; + return TT.isOSWindows() ? X86::RCX : X86::RDI; } -unsigned -ExegesisX86Target::getLoopCounterRegister(const llvm::Triple &TT) const { +unsigned ExegesisX86Target::getLoopCounterRegister(const Triple &TT) const { if (!TT.isArch64Bit()) { return 0; } @@ -619,16 +612,15 @@ ExegesisX86Target::getLoopCounterRegister(const llvm::Triple &TT) const { } void ExegesisX86Target::randomizeMCOperand( - const Instruction &Instr, const Variable &Var, - llvm::MCOperand &AssignedValue, - const llvm::BitVector &ForbiddenRegs) const { + const Instruction &Instr, const Variable &Var, MCOperand &AssignedValue, + const BitVector &ForbiddenRegs) const { ExegesisTarget::randomizeMCOperand(Instr, Var, AssignedValue, ForbiddenRegs); const Operand &Op = Instr.getPrimaryOperand(Var); switch (Op.getExplicitOperandInfo().OperandType) { - case llvm::X86::OperandType::OPERAND_COND_CODE: - AssignedValue = llvm::MCOperand::createImm( - randomIndex(llvm::X86::CondCode::LAST_VALID_COND)); + case X86::OperandType::OPERAND_COND_CODE: + AssignedValue = + MCOperand::createImm(randomIndex(X86::CondCode::LAST_VALID_COND)); break; default: break; @@ -658,7 +650,7 @@ void ExegesisX86Target::fillMemoryOperands(InstructionTemplate &IT, void ExegesisX86Target::decrementLoopCounterAndJump( MachineBasicBlock &MBB, MachineBasicBlock &TargetMBB, - const llvm::MCInstrInfo &MII) const { + const MCInstrInfo &MII) const { BuildMI(&MBB, DebugLoc(), MII.get(X86::ADD64ri8)) .addDef(kLoopCounterReg) .addUse(kLoopCounterReg) @@ -668,45 +660,44 @@ void ExegesisX86Target::decrementLoopCounterAndJump( .addImm(X86::COND_NE); } -std::vector<llvm::MCInst> -ExegesisX86Target::setRegTo(const llvm::MCSubtargetInfo &STI, unsigned Reg, - const llvm::APInt &Value) const { - if (llvm::X86::GR8RegClass.contains(Reg)) +std::vector<MCInst> ExegesisX86Target::setRegTo(const MCSubtargetInfo &STI, + unsigned Reg, + const APInt &Value) const { + if (X86::GR8RegClass.contains(Reg)) return {loadImmediate(Reg, 8, Value)}; - if (llvm::X86::GR16RegClass.contains(Reg)) + if (X86::GR16RegClass.contains(Reg)) return {loadImmediate(Reg, 16, Value)}; - if (llvm::X86::GR32RegClass.contains(Reg)) + if (X86::GR32RegClass.contains(Reg)) return {loadImmediate(Reg, 32, Value)}; - if (llvm::X86::GR64RegClass.contains(Reg)) + if (X86::GR64RegClass.contains(Reg)) return {loadImmediate(Reg, 64, Value)}; ConstantInliner CI(Value); - if (llvm::X86::VR64RegClass.contains(Reg)) - return CI.loadAndFinalize(Reg, 64, llvm::X86::MMX_MOVQ64rm); - if (llvm::X86::VR128XRegClass.contains(Reg)) { - if (STI.getFeatureBits()[llvm::X86::FeatureAVX512]) - return CI.loadAndFinalize(Reg, 128, llvm::X86::VMOVDQU32Z128rm); - if (STI.getFeatureBits()[llvm::X86::FeatureAVX]) - return CI.loadAndFinalize(Reg, 128, llvm::X86::VMOVDQUrm); - return CI.loadAndFinalize(Reg, 128, llvm::X86::MOVDQUrm); + if (X86::VR64RegClass.contains(Reg)) + return CI.loadAndFinalize(Reg, 64, X86::MMX_MOVQ64rm); + if (X86::VR128XRegClass.contains(Reg)) { + if (STI.getFeatureBits()[X86::FeatureAVX512]) + return CI.loadAndFinalize(Reg, 128, X86::VMOVDQU32Z128rm); + if (STI.getFeatureBits()[X86::FeatureAVX]) + return CI.loadAndFinalize(Reg, 128, X86::VMOVDQUrm); + return CI.loadAndFinalize(Reg, 128, X86::MOVDQUrm); } - if (llvm::X86::VR256XRegClass.contains(Reg)) { - if (STI.getFeatureBits()[llvm::X86::FeatureAVX512]) - return CI.loadAndFinalize(Reg, 256, llvm::X86::VMOVDQU32Z256rm); - if (STI.getFeatureBits()[llvm::X86::FeatureAVX]) - return CI.loadAndFinalize(Reg, 256, llvm::X86::VMOVDQUYrm); + if (X86::VR256XRegClass.contains(Reg)) { + if (STI.getFeatureBits()[X86::FeatureAVX512]) + return CI.loadAndFinalize(Reg, 256, X86::VMOVDQU32Z256rm); + if (STI.getFeatureBits()[X86::FeatureAVX]) + return CI.loadAndFinalize(Reg, 256, X86::VMOVDQUYrm); } - if (llvm::X86::VR512RegClass.contains(Reg)) - if (STI.getFeatureBits()[llvm::X86::FeatureAVX512]) - return CI.loadAndFinalize(Reg, 512, llvm::X86::VMOVDQU32Zrm); - if (llvm::X86::RSTRegClass.contains(Reg)) { + if (X86::VR512RegClass.contains(Reg)) + if (STI.getFeatureBits()[X86::FeatureAVX512]) + return CI.loadAndFinalize(Reg, 512, X86::VMOVDQU32Zrm); + if (X86::RSTRegClass.contains(Reg)) { return CI.loadX87STAndFinalize(Reg); } - if (llvm::X86::RFP32RegClass.contains(Reg) || - llvm::X86::RFP64RegClass.contains(Reg) || - llvm::X86::RFP80RegClass.contains(Reg)) { + if (X86::RFP32RegClass.contains(Reg) || X86::RFP64RegClass.contains(Reg) || + X86::RFP80RegClass.contains(Reg)) { return CI.loadX87FPAndFinalize(Reg); } - if (Reg == llvm::X86::EFLAGS) + if (Reg == X86::EFLAGS) return CI.popFlagAndFinalize(); return {}; // Not yet implemented. } |
