1 files changed, 15 insertions, 16 deletions
diff --git a/llvm/tools/llvm-exegesis/lib/PowerPC/Target.cpp b/llvm/tools/llvm-exegesis/lib/PowerPC/Target.cpp
index 0f8162d2296..567d62031f1 100644
--- a/llvm/tools/llvm-exegesis/lib/PowerPC/Target.cpp
+++ b/llvm/tools/llvm-exegesis/lib/PowerPC/Target.cpp
@@ -22,11 +22,10 @@ public:
   ExegesisPowerPCTarget() : ExegesisTarget(PPCCpuPfmCounters) {}
 
 private:
-  std::vector<llvm::MCInst> setRegTo(const llvm::MCSubtargetInfo &STI,
-                                     unsigned Reg,
-                                     const llvm::APInt &Value) const override;
-  bool matchesArch(llvm::Triple::ArchType Arch) const override {
-    return Arch == llvm::Triple::ppc64le;
+  std::vector<MCInst> setRegTo(const MCSubtargetInfo &STI, unsigned Reg,
+                               const APInt &Value) const override;
+  bool matchesArch(Triple::ArchType Arch) const override {
+    return Arch == Triple::ppc64le;
   }
 };
 } // end anonymous namespace
@@ -34,31 +33,31 @@ private:
 static unsigned getLoadImmediateOpcode(unsigned RegBitWidth) {
   switch (RegBitWidth) {
   case 32:
-    return llvm::PPC::LI;
+    return PPC::LI;
   case 64:
-    return llvm::PPC::LI8;
+    return PPC::LI8;
   }
   llvm_unreachable("Invalid Value Width");
 }
 
 // Generates instruction to load an immediate value into a register.
-static llvm::MCInst loadImmediate(unsigned Reg, unsigned RegBitWidth,
-                                  const llvm::APInt &Value) {
+static MCInst loadImmediate(unsigned Reg, unsigned RegBitWidth,
+                            const APInt &Value) {
   if (Value.getBitWidth() > RegBitWidth)
     llvm_unreachable("Value must fit in the Register");
-  return llvm::MCInstBuilder(getLoadImmediateOpcode(RegBitWidth))
+  return MCInstBuilder(getLoadImmediateOpcode(RegBitWidth))
       .addReg(Reg)
       .addImm(Value.getZExtValue());
 }
 
-std::vector<llvm::MCInst>
-ExegesisPowerPCTarget::setRegTo(const llvm::MCSubtargetInfo &STI, unsigned Reg,
-                                const llvm::APInt &Value) const {
-  if (llvm::PPC::GPRCRegClass.contains(Reg))
+std::vector<MCInst> ExegesisPowerPCTarget::setRegTo(const MCSubtargetInfo &STI,
+                                                    unsigned Reg,
+                                                    const APInt &Value) const {
+  if (PPC::GPRCRegClass.contains(Reg))
     return {loadImmediate(Reg, 32, Value)};
-  if (llvm::PPC::G8RCRegClass.contains(Reg))
+  if (PPC::G8RCRegClass.contains(Reg))
     return {loadImmediate(Reg, 64, Value)};
-  llvm::errs() << "setRegTo is not implemented, results will be unreliable\n";
+  errs() << "setRegTo is not implemented, results will be unreliable\n";
   return {};
 }