1 files changed, 52 insertions, 7 deletions

diff --git a/llvm/tools/llvm-exegesis/lib/MCInstrDescView.h b/llvm/tools/llvm-exegesis/lib/MCInstrDescView.h
index df360f5de4e..967d9643529 100644
--- a/llvm/tools/llvm-exegesis/lib/MCInstrDescView.h
+++ b/llvm/tools/llvm-exegesis/lib/MCInstrDescView.h
@@ -30,11 +30,18 @@
 
 namespace exegesis {
 
-struct Operand; // forward declaration.
-
 // A variable represents the value associated to an Operand or a set of Operands
 // if they are tied together.
 struct Variable {
+  // Returns the index of this Variable inside Instruction's Variable.
+  unsigned getIndex() const;
+
+  // Returns the index of the Operand linked to this Variable.
+  unsigned getPrimaryOperandIndex() const;
+
+  // Returns whether this Variable has more than one Operand linked to it.
+  bool hasTiedOperands() const;
+
   // The indices of the operands tied to this Variable.
   llvm::SmallVector<unsigned, 2> TiedOperands;
   llvm::MCOperand AssignedValue;
@@ -45,7 +52,6 @@ struct Variable {
 
 // MCOperandInfo can only represents Explicit operands. This object gives a
 // uniform view of Implicit and Explicit Operands.
-//
 // - Index: can be used to refer to MCInstrDesc::operands for Explicit operands.
 // - Tracker: is set for Register Operands and is used to keep track of possible
 // registers and the registers reachable from them (aliasing registers).
@@ -56,10 +62,26 @@ struct Variable {
 // - VariableIndex: the index of the Variable holding the value for this Operand
 // or -1 if this operand is implicit.
 struct Operand {
+  bool getIndex() const;
+  bool isExplicit() const;
+  bool isImplicit() const;
+  bool isImplicitReg() const;
+  bool isDef() const;
+  bool isUse() const;
+  bool isReg() const;
+  bool isTied() const;
+  bool isVariable() const;
+  bool isMemory() const;
+  bool isImmediate() const;
+  int getTiedToIndex() const;
+  int getVariableIndex() const;
+  unsigned getImplicitReg() const;
+  const RegisterAliasingTracker &getRegisterAliasing() const;
+  const llvm::MCOperandInfo &getExplicitOperandInfo() const;
+
+  // Please use the accessors above and not the following fields.
   unsigned Index = 0;
   bool IsDef = false;
-  bool IsMem = false;
-  bool IsExplicit = false;
   const RegisterAliasingTracker *Tracker = nullptr; // Set for Register Op.
   const llvm::MCOperandInfo *Info = nullptr;        // Set for Explicit Op.
   int TiedToIndex = -1;                             // Set for Reg&Explicit Op.
@@ -73,13 +95,36 @@ struct Instruction {
   Instruction(const llvm::MCInstrDesc &MCInstrDesc,
               const RegisterAliasingTrackerCache &ATC);
 
+  // Returns the Operand linked to this Variable.
+  // In case the Variable is tied, the primary (i.e. Def) Operand is returned.
+  const Operand &getPrimaryOperand(const Variable &Var) const;
+
+  // Returns whether this instruction has Memory Operands.
+  // Repeating this instruction executes sequentially with an instruction that
+  // reads or write the same memory region.
   bool hasMemoryOperands() const;
 
+  // Whether this instruction is self aliasing through its implicit registers.
+  // Repeating this instruction is guaranteed to executes sequentially.
+  bool hasAliasingImplicitRegisters() const;
+
+  // Whether this instruction is self aliasing through its tied registers.
+  // Repeating this instruction is guaranteed to executes sequentially.
+  bool hasTiedRegisters() const;
+
+  // Whether this instruction is self aliasing through some registers.
+  // Repeating this instruction may execute sequentially by picking aliasing
+  // Use and Def registers. It may also execute in parallel by picking non
+  // aliasing Use and Def registers.
+  bool hasAliasingRegisters() const;
+
   const llvm::MCInstrDesc *Description; // Never nullptr.
   llvm::SmallVector<Operand, 8> Operands;
   llvm::SmallVector<Variable, 4> Variables;
-  llvm::BitVector DefRegisters; // The union of the aliased def registers.
-  llvm::BitVector UseRegisters; // The union of the aliased use registers.
+  llvm::BitVector ImplDefRegs; // The set of aliased implicit def registers.
+  llvm::BitVector ImplUseRegs; // The set of aliased implicit use registers.
+  llvm::BitVector AllDefRegs;  // The set of all aliased def registers.
+  llvm::BitVector AllUseRegs;  // The set of all aliased use registers.
 };
 
 // Represents the assignment of a Register to an Operand.