1 files changed, 12 insertions, 12 deletions

diff --git a/llvm/tools/llvm-exegesis/lib/Latency.cpp b/llvm/tools/llvm-exegesis/lib/Latency.cpp
index 45a0e7e362d..7030658a460 100644
--- a/llvm/tools/llvm-exegesis/lib/Latency.cpp
+++ b/llvm/tools/llvm-exegesis/lib/Latency.cpp
@@ -37,8 +37,8 @@ struct ExecutionClass {
 
 static constexpr size_t kMaxAliasingInstructions = 10;
 
-static std::vector<Instruction>
-computeAliasingInstructions(const LLVMState &State, const Instruction &Instr,
+static std::vector<const Instruction *>
+computeAliasingInstructions(const LLVMState &State, const Instruction *Instr,
                             size_t MaxAliasingInstructions,
                             const BitVector &ForbiddenRegisters) {
   // Randomly iterate the set of instructions.
@@ -47,15 +47,15 @@ computeAliasingInstructions(const LLVMState &State, const Instruction &Instr,
   std::iota(Opcodes.begin(), Opcodes.end(), 0U);
   std::shuffle(Opcodes.begin(), Opcodes.end(), randomGenerator());
 
-  std::vector<Instruction> AliasingInstructions;
+  std::vector<const Instruction *> AliasingInstructions;
   for (const unsigned OtherOpcode : Opcodes) {
-    if (OtherOpcode == Instr.Description->getOpcode())
+    if (OtherOpcode == Instr->Description.getOpcode())
       continue;
     const Instruction &OtherInstr = State.getIC().getInstr(OtherOpcode);
     if (OtherInstr.hasMemoryOperands())
       continue;
-    if (Instr.hasAliasingRegistersThrough(OtherInstr, ForbiddenRegisters))
-      AliasingInstructions.push_back(OtherInstr);
+    if (Instr->hasAliasingRegistersThrough(OtherInstr, ForbiddenRegisters))
+      AliasingInstructions.push_back(&OtherInstr);
     if (AliasingInstructions.size() >= MaxAliasingInstructions)
       break;
   }
@@ -81,7 +81,7 @@ static ExecutionMode getExecutionModes(const Instruction &Instr,
 }
 
 static void appendCodeTemplates(const LLVMState &State,
-                                const Instruction &Instr,
+                                const Instruction *Instr,
                                 const BitVector &ForbiddenRegisters,
                                 ExecutionMode ExecutionModeBit,
                                 StringRef ExecutionClassDescription,
@@ -109,7 +109,7 @@ static void appendCodeTemplates(const LLVMState &State,
   case ExecutionMode::SERIAL_VIA_EXPLICIT_REGS: {
     // Making the execution of this instruction serial by selecting one def
     // register to alias with one use register.
-    const AliasingConfigurations SelfAliasing(Instr, Instr);
+    const AliasingConfigurations SelfAliasing(*Instr, *Instr);
     assert(!SelfAliasing.empty() && !SelfAliasing.hasImplicitAliasing() &&
            "Instr must alias itself explicitly");
     InstructionTemplate IT(Instr);
@@ -125,10 +125,10 @@ static void appendCodeTemplates(const LLVMState &State,
   }
   case ExecutionMode::SERIAL_VIA_NON_MEMORY_INSTR: {
     // Select back-to-back non-memory instruction.
-    for (const auto OtherInstr : computeAliasingInstructions(
+    for (const auto *OtherInstr : computeAliasingInstructions(
              State, Instr, kMaxAliasingInstructions, ForbiddenRegisters)) {
-      const AliasingConfigurations Forward(Instr, OtherInstr);
-      const AliasingConfigurations Back(OtherInstr, Instr);
+      const AliasingConfigurations Forward(*Instr, *OtherInstr);
+      const AliasingConfigurations Back(*OtherInstr, *Instr);
       InstructionTemplate ThisIT(Instr);
       InstructionTemplate OtherIT(OtherInstr);
       if (!Forward.hasImplicitAliasing())
@@ -158,7 +158,7 @@ LatencySnippetGenerator::generateCodeTemplates(
   const ExecutionMode EM = getExecutionModes(Instr, ForbiddenRegisters);
   for (const auto EC : kExecutionClasses) {
     for (const auto ExecutionModeBit : getExecutionModeBits(EM & EC.Mask))
-      appendCodeTemplates(State, Instr, ForbiddenRegisters, ExecutionModeBit,
+      appendCodeTemplates(State, &Instr, ForbiddenRegisters, ExecutionModeBit,
                           EC.Description, Results);
     if (!Results.empty())
       break;