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-rw-r--r--llvm/test/CodeGen/AArch64/load-combine-big-endian.ll12
-rw-r--r--llvm/test/CodeGen/AArch64/load-combine.ll12
-rw-r--r--llvm/test/CodeGen/ARM/load-combine-big-endian.ll38
-rw-r--r--llvm/test/CodeGen/ARM/load-combine.ll36
-rw-r--r--llvm/test/CodeGen/X86/load-combine.ll24
5 files changed, 42 insertions, 80 deletions
diff --git a/llvm/test/CodeGen/AArch64/load-combine-big-endian.ll b/llvm/test/CodeGen/AArch64/load-combine-big-endian.ll
index 426bb880ed1..19de95198c1 100644
--- a/llvm/test/CodeGen/AArch64/load-combine-big-endian.ll
+++ b/llvm/test/CodeGen/AArch64/load-combine-big-endian.ll
@@ -445,10 +445,9 @@ define i32 @load_i32_by_i8_base_offset_index_2(i8* %arg, i32 %i) {
define i32 @zext_load_i32_by_i8(i32* %arg) {
; CHECK-LABEL: zext_load_i32_by_i8:
; CHECK: // %bb.0:
-; CHECK-NEXT: ldrb w8, [x0]
-; CHECK-NEXT: ldrb w9, [x0, #1]
-; CHECK-NEXT: bfi w8, w9, #8, #8
-; CHECK-NEXT: mov w0, w8
+; CHECK-NEXT: ldrh w8, [x0]
+; CHECK-NEXT: lsl w8, w8, #16
+; CHECK-NEXT: rev w0, w8
; CHECK-NEXT: ret
%tmp = bitcast i32* %arg to i8*
@@ -515,10 +514,7 @@ define i32 @zext_load_i32_by_i8_shl_16(i32* %arg) {
define i32 @zext_load_i32_by_i8_bswap(i32* %arg) {
; CHECK-LABEL: zext_load_i32_by_i8_bswap:
; CHECK: // %bb.0:
-; CHECK-NEXT: ldrb w8, [x0, #1]
-; CHECK-NEXT: ldrb w9, [x0]
-; CHECK-NEXT: bfi w8, w9, #8, #8
-; CHECK-NEXT: mov w0, w8
+; CHECK-NEXT: ldrh w0, [x0]
; CHECK-NEXT: ret
%tmp = bitcast i32* %arg to i8*
diff --git a/llvm/test/CodeGen/AArch64/load-combine.ll b/llvm/test/CodeGen/AArch64/load-combine.ll
index 906646cda15..066ecb21dc1 100644
--- a/llvm/test/CodeGen/AArch64/load-combine.ll
+++ b/llvm/test/CodeGen/AArch64/load-combine.ll
@@ -431,10 +431,7 @@ define i32 @load_i32_by_i8_base_offset_index_2(i8* %arg, i32 %i) {
define i32 @zext_load_i32_by_i8(i32* %arg) {
; CHECK-LABEL: zext_load_i32_by_i8:
; CHECK: // %bb.0:
-; CHECK-NEXT: ldrb w8, [x0]
-; CHECK-NEXT: ldrb w9, [x0, #1]
-; CHECK-NEXT: bfi w8, w9, #8, #8
-; CHECK-NEXT: mov w0, w8
+; CHECK-NEXT: ldrh w0, [x0]
; CHECK-NEXT: ret
%tmp = bitcast i32* %arg to i8*
@@ -501,10 +498,9 @@ define i32 @zext_load_i32_by_i8_shl_16(i32* %arg) {
define i32 @zext_load_i32_by_i8_bswap(i32* %arg) {
; CHECK-LABEL: zext_load_i32_by_i8_bswap:
; CHECK: // %bb.0:
-; CHECK-NEXT: ldrb w8, [x0, #1]
-; CHECK-NEXT: ldrb w9, [x0]
-; CHECK-NEXT: bfi w8, w9, #8, #8
-; CHECK-NEXT: mov w0, w8
+; CHECK-NEXT: ldrh w8, [x0]
+; CHECK-NEXT: lsl w8, w8, #16
+; CHECK-NEXT: rev w0, w8
; CHECK-NEXT: ret
%tmp = bitcast i32* %arg to i8*
diff --git a/llvm/test/CodeGen/ARM/load-combine-big-endian.ll b/llvm/test/CodeGen/ARM/load-combine-big-endian.ll
index d045f1f96ee..0ed85501a7b 100644
--- a/llvm/test/CodeGen/ARM/load-combine-big-endian.ll
+++ b/llvm/test/CodeGen/ARM/load-combine-big-endian.ll
@@ -824,25 +824,23 @@ define i32 @zext_load_i32_by_i8(i32* %arg) {
;
; CHECK-ARMv6-LABEL: zext_load_i32_by_i8:
; CHECK-ARMv6: @ %bb.0:
-; CHECK-ARMv6-NEXT: ldrb r1, [r0]
-; CHECK-ARMv6-NEXT: ldrb r0, [r0, #1]
-; CHECK-ARMv6-NEXT: orr r0, r1, r0, lsl #8
+; CHECK-ARMv6-NEXT: ldrh r0, [r0]
+; CHECK-ARMv6-NEXT: lsl r0, r0, #16
+; CHECK-ARMv6-NEXT: rev r0, r0
; CHECK-ARMv6-NEXT: bx lr
;
; CHECK-THUMBv6-LABEL: zext_load_i32_by_i8:
; CHECK-THUMBv6: @ %bb.0:
-; CHECK-THUMBv6-NEXT: ldrb r1, [r0]
-; CHECK-THUMBv6-NEXT: ldrb r0, [r0, #1]
-; CHECK-THUMBv6-NEXT: lsls r0, r0, #8
-; CHECK-THUMBv6-NEXT: adds r0, r0, r1
+; CHECK-THUMBv6-NEXT: ldrh r0, [r0]
+; CHECK-THUMBv6-NEXT: lsls r0, r0, #16
+; CHECK-THUMBv6-NEXT: rev r0, r0
; CHECK-THUMBv6-NEXT: bx lr
;
; CHECK-THUMBv7-LABEL: zext_load_i32_by_i8:
; CHECK-THUMBv7: @ %bb.0:
-; CHECK-THUMBv7-NEXT: ldrb r1, [r0]
-; CHECK-THUMBv7-NEXT: ldrb r0, [r0, #1]
-; CHECK-THUMBv7-NEXT: lsls r0, r0, #8
-; CHECK-THUMBv7-NEXT: adds r0, r0, r1
+; CHECK-THUMBv7-NEXT: ldrh r0, [r0]
+; CHECK-THUMBv7-NEXT: lsls r0, r0, #16
+; CHECK-THUMBv7-NEXT: rev r0, r0
; CHECK-THUMBv7-NEXT: bx lr
%tmp = bitcast i32* %arg to i8*
@@ -962,32 +960,22 @@ define i32 @zext_load_i32_by_i8_shl_16(i32* %arg) {
define i32 @zext_load_i32_by_i8_bswap(i32* %arg) {
; CHECK-LABEL: zext_load_i32_by_i8_bswap:
; CHECK: @ %bb.0:
-; CHECK-NEXT: ldrb r1, [r0]
-; CHECK-NEXT: ldrb r0, [r0, #1]
-; CHECK-NEXT: orr r0, r0, r1, lsl #8
+; CHECK-NEXT: ldrh r0, [r0]
; CHECK-NEXT: mov pc, lr
;
; CHECK-ARMv6-LABEL: zext_load_i32_by_i8_bswap:
; CHECK-ARMv6: @ %bb.0:
-; CHECK-ARMv6-NEXT: ldrb r1, [r0]
-; CHECK-ARMv6-NEXT: ldrb r0, [r0, #1]
-; CHECK-ARMv6-NEXT: orr r0, r0, r1, lsl #8
+; CHECK-ARMv6-NEXT: ldrh r0, [r0]
; CHECK-ARMv6-NEXT: bx lr
;
; CHECK-THUMBv6-LABEL: zext_load_i32_by_i8_bswap:
; CHECK-THUMBv6: @ %bb.0:
-; CHECK-THUMBv6-NEXT: ldrb r1, [r0, #1]
-; CHECK-THUMBv6-NEXT: ldrb r0, [r0]
-; CHECK-THUMBv6-NEXT: lsls r0, r0, #8
-; CHECK-THUMBv6-NEXT: adds r0, r0, r1
+; CHECK-THUMBv6-NEXT: ldrh r0, [r0]
; CHECK-THUMBv6-NEXT: bx lr
;
; CHECK-THUMBv7-LABEL: zext_load_i32_by_i8_bswap:
; CHECK-THUMBv7: @ %bb.0:
-; CHECK-THUMBv7-NEXT: ldrb r1, [r0, #1]
-; CHECK-THUMBv7-NEXT: ldrb r0, [r0]
-; CHECK-THUMBv7-NEXT: lsls r0, r0, #8
-; CHECK-THUMBv7-NEXT: adds r0, r0, r1
+; CHECK-THUMBv7-NEXT: ldrh r0, [r0]
; CHECK-THUMBv7-NEXT: bx lr
%tmp = bitcast i32* %arg to i8*
diff --git a/llvm/test/CodeGen/ARM/load-combine.ll b/llvm/test/CodeGen/ARM/load-combine.ll
index d173a098b9b..bf03898c891 100644
--- a/llvm/test/CodeGen/ARM/load-combine.ll
+++ b/llvm/test/CodeGen/ARM/load-combine.ll
@@ -734,31 +734,22 @@ define i32 @load_i32_by_i8_base_offset_index_2(i8* %arg, i32 %i) {
define i32 @zext_load_i32_by_i8(i32* %arg) {
; CHECK-LABEL: zext_load_i32_by_i8:
; CHECK: @ %bb.0:
-; CHECK-NEXT: ldrb r1, [r0]
-; CHECK-NEXT: ldrb r0, [r0, #1]
-; CHECK-NEXT: orr r0, r1, r0, lsl #8
+; CHECK-NEXT: ldrh r0, [r0]
; CHECK-NEXT: mov pc, lr
;
; CHECK-ARMv6-LABEL: zext_load_i32_by_i8:
; CHECK-ARMv6: @ %bb.0:
-; CHECK-ARMv6-NEXT: ldrb r1, [r0]
-; CHECK-ARMv6-NEXT: ldrb r0, [r0, #1]
-; CHECK-ARMv6-NEXT: orr r0, r1, r0, lsl #8
+; CHECK-ARMv6-NEXT: ldrh r0, [r0]
; CHECK-ARMv6-NEXT: bx lr
;
; CHECK-THUMBv6-LABEL: zext_load_i32_by_i8:
; CHECK-THUMBv6: @ %bb.0:
-; CHECK-THUMBv6-NEXT: ldrb r1, [r0]
-; CHECK-THUMBv6-NEXT: ldrb r0, [r0, #1]
-; CHECK-THUMBv6-NEXT: lsls r0, r0, #8
-; CHECK-THUMBv6-NEXT: adds r0, r0, r1
+; CHECK-THUMBv6-NEXT: ldrh r0, [r0]
; CHECK-THUMBv6-NEXT: bx lr
;
; CHECK-THUMBv7-LABEL: zext_load_i32_by_i8:
; CHECK-THUMBv7: @ %bb.0:
-; CHECK-THUMBv7-NEXT: ldrb r1, [r0]
-; CHECK-THUMBv7-NEXT: ldrb r0, [r0, #1]
-; CHECK-THUMBv7-NEXT: orr.w r0, r1, r0, lsl #8
+; CHECK-THUMBv7-NEXT: ldrh r0, [r0]
; CHECK-THUMBv7-NEXT: bx lr
%tmp = bitcast i32* %arg to i8*
@@ -883,24 +874,23 @@ define i32 @zext_load_i32_by_i8_bswap(i32* %arg) {
;
; CHECK-ARMv6-LABEL: zext_load_i32_by_i8_bswap:
; CHECK-ARMv6: @ %bb.0:
-; CHECK-ARMv6-NEXT: ldrb r1, [r0]
-; CHECK-ARMv6-NEXT: ldrb r0, [r0, #1]
-; CHECK-ARMv6-NEXT: orr r0, r0, r1, lsl #8
+; CHECK-ARMv6-NEXT: ldrh r0, [r0]
+; CHECK-ARMv6-NEXT: lsl r0, r0, #16
+; CHECK-ARMv6-NEXT: rev r0, r0
; CHECK-ARMv6-NEXT: bx lr
;
; CHECK-THUMBv6-LABEL: zext_load_i32_by_i8_bswap:
; CHECK-THUMBv6: @ %bb.0:
-; CHECK-THUMBv6-NEXT: ldrb r1, [r0, #1]
-; CHECK-THUMBv6-NEXT: ldrb r0, [r0]
-; CHECK-THUMBv6-NEXT: lsls r0, r0, #8
-; CHECK-THUMBv6-NEXT: adds r0, r0, r1
+; CHECK-THUMBv6-NEXT: ldrh r0, [r0]
+; CHECK-THUMBv6-NEXT: lsls r0, r0, #16
+; CHECK-THUMBv6-NEXT: rev r0, r0
; CHECK-THUMBv6-NEXT: bx lr
;
; CHECK-THUMBv7-LABEL: zext_load_i32_by_i8_bswap:
; CHECK-THUMBv7: @ %bb.0:
-; CHECK-THUMBv7-NEXT: ldrb r1, [r0]
-; CHECK-THUMBv7-NEXT: ldrb r0, [r0, #1]
-; CHECK-THUMBv7-NEXT: orr.w r0, r0, r1, lsl #8
+; CHECK-THUMBv7-NEXT: ldrh r0, [r0]
+; CHECK-THUMBv7-NEXT: lsls r0, r0, #16
+; CHECK-THUMBv7-NEXT: rev r0, r0
; CHECK-THUMBv7-NEXT: bx lr
%tmp = bitcast i32* %arg to i8*
diff --git a/llvm/test/CodeGen/X86/load-combine.ll b/llvm/test/CodeGen/X86/load-combine.ll
index 1d08ee06531..5184e99d018 100644
--- a/llvm/test/CodeGen/X86/load-combine.ll
+++ b/llvm/test/CodeGen/X86/load-combine.ll
@@ -1119,18 +1119,12 @@ define i32 @zext_load_i32_by_i8(i32* %arg) {
; CHECK-LABEL: zext_load_i32_by_i8:
; CHECK: # %bb.0:
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
-; CHECK-NEXT: movzbl (%eax), %ecx
-; CHECK-NEXT: movzbl 1(%eax), %eax
-; CHECK-NEXT: shll $8, %eax
-; CHECK-NEXT: orl %ecx, %eax
+; CHECK-NEXT: movzwl (%eax), %eax
; CHECK-NEXT: retl
;
; CHECK64-LABEL: zext_load_i32_by_i8:
; CHECK64: # %bb.0:
-; CHECK64-NEXT: movzbl (%rdi), %ecx
-; CHECK64-NEXT: movzbl 1(%rdi), %eax
-; CHECK64-NEXT: shll $8, %eax
-; CHECK64-NEXT: orl %ecx, %eax
+; CHECK64-NEXT: movzwl (%rdi), %eax
; CHECK64-NEXT: retq
%tmp = bitcast i32* %arg to i8*
%tmp1 = getelementptr inbounds i8, i8* %tmp, i32 0
@@ -1218,18 +1212,16 @@ define i32 @zext_load_i32_by_i8_bswap(i32* %arg) {
; CHECK-LABEL: zext_load_i32_by_i8_bswap:
; CHECK: # %bb.0:
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
-; CHECK-NEXT: movzbl 1(%eax), %ecx
-; CHECK-NEXT: movzbl (%eax), %eax
-; CHECK-NEXT: shll $8, %eax
-; CHECK-NEXT: orl %ecx, %eax
+; CHECK-NEXT: movzwl (%eax), %eax
+; CHECK-NEXT: shll $16, %eax
+; CHECK-NEXT: bswapl %eax
; CHECK-NEXT: retl
;
; CHECK64-LABEL: zext_load_i32_by_i8_bswap:
; CHECK64: # %bb.0:
-; CHECK64-NEXT: movzbl 1(%rdi), %ecx
-; CHECK64-NEXT: movzbl (%rdi), %eax
-; CHECK64-NEXT: shll $8, %eax
-; CHECK64-NEXT: orl %ecx, %eax
+; CHECK64-NEXT: movzwl (%rdi), %eax
+; CHECK64-NEXT: shll $16, %eax
+; CHECK64-NEXT: bswapl %eax
; CHECK64-NEXT: retq
%tmp = bitcast i32* %arg to i8*
%tmp1 = getelementptr inbounds i8, i8* %tmp, i32 1
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