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-rw-r--r--llvm/test/CodeGen/X86/avx512-i1test.ll7
-rw-r--r--llvm/test/CodeGen/X86/fast-isel-select-cmov.ll3
-rw-r--r--llvm/test/CodeGen/X86/pr28173.ll95
-rw-r--r--llvm/test/CodeGen/X86/xaluo.ll5
4 files changed, 88 insertions, 22 deletions
diff --git a/llvm/test/CodeGen/X86/avx512-i1test.ll b/llvm/test/CodeGen/X86/avx512-i1test.ll
index a40261cb5fa..69fafdfff9a 100644
--- a/llvm/test/CodeGen/X86/avx512-i1test.ll
+++ b/llvm/test/CodeGen/X86/avx512-i1test.ll
@@ -66,15 +66,14 @@ L_30: ; preds = %bb51, %L_10
define i64 @func2(i1 zeroext %i, i32 %j) {
; CHECK-LABEL: func2:
; CHECK: # BB#0: # %entry
+; CHECK-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
; CHECK-NEXT: testl %esi, %esi
; CHECK-NEXT: je .LBB1_1
; CHECK-NEXT: # BB#2: # %if.then
; CHECK-NEXT: jmp bar # TAILCALL
; CHECK-NEXT: .LBB1_1: # %return
-; CHECK-NEXT: andl $1, %edi
-; CHECK-NEXT: kmovw %edi, %k0
-; CHECK-NEXT: kmovw %k0, %eax
-; CHECK-NEXT: orq $-2, %rax
+; CHECK-NEXT: orq $-2, %rdi
+; CHECK-NEXT: movq %rdi, %rax
; CHECK-NEXT: retq
entry:
%tobool = icmp eq i32 %j, 0
diff --git a/llvm/test/CodeGen/X86/fast-isel-select-cmov.ll b/llvm/test/CodeGen/X86/fast-isel-select-cmov.ll
index a6de1e06b80..290bcaaf4a2 100644
--- a/llvm/test/CodeGen/X86/fast-isel-select-cmov.ll
+++ b/llvm/test/CodeGen/X86/fast-isel-select-cmov.ll
@@ -15,7 +15,6 @@ define zeroext i16 @select_cmov_i16(i1 zeroext %cond, i16 zeroext %a, i16 zeroex
;
; AVX512-LABEL: select_cmov_i16:
; AVX512: ## BB#0:
-; AVX512-NEXT: andl $1, %edi
; AVX512-NEXT: kmovw %edi, %k0
; AVX512-NEXT: kortestw %k0, %k0
; AVX512-NEXT: cmovew %dx, %si
@@ -47,7 +46,6 @@ define i32 @select_cmov_i32(i1 zeroext %cond, i32 %a, i32 %b) {
;
; AVX512-LABEL: select_cmov_i32:
; AVX512: ## BB#0:
-; AVX512-NEXT: andl $1, %edi
; AVX512-NEXT: kmovw %edi, %k0
; AVX512-NEXT: kortestw %k0, %k0
; AVX512-NEXT: cmovel %edx, %esi
@@ -79,7 +77,6 @@ define i64 @select_cmov_i64(i1 zeroext %cond, i64 %a, i64 %b) {
;
; AVX512-LABEL: select_cmov_i64:
; AVX512: ## BB#0:
-; AVX512-NEXT: andl $1, %edi
; AVX512-NEXT: kmovw %edi, %k0
; AVX512-NEXT: kortestw %k0, %k0
; AVX512-NEXT: cmoveq %rdx, %rsi
diff --git a/llvm/test/CodeGen/X86/pr28173.ll b/llvm/test/CodeGen/X86/pr28173.ll
index 81c10bb3757..db7d3335215 100644
--- a/llvm/test/CodeGen/X86/pr28173.ll
+++ b/llvm/test/CodeGen/X86/pr28173.ll
@@ -1,16 +1,20 @@
-; RUN: llc -mattr=+avx512f < %s | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mattr=+avx512f | FileCheck %s --check-prefix=CHECK --check-prefix=KNL
+; RUN: llc < %s -mattr=+avx512f,+avx512vl,+avx512bw,+avx512dq | FileCheck %s --check-prefix=CHECK --check-prefix=SKX
+
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"
; Note that the kmovs should really *not* appear in the output, this is an
; artifact of the current poor lowering. This is tracked by PR28175.
-; CHECK-LABEL: @foo64
-; CHECK: kmov
-; CHECK: kmov
-; CHECK: orq $-2, %rax
-; CHECK: ret
-define i64 @foo64(i1 zeroext %i, i32 %j) #0 {
+define i64 @foo64(i1 zeroext %i) #0 {
+; CHECK-LABEL: foo64:
+; CHECK: # BB#0:
+; CHECK-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
+; CHECK-NEXT: orq $-2, %rdi
+; CHECK-NEXT: movq %rdi, %rax
+; CHECK-NEXT: retq
br label %bb
bb:
@@ -22,12 +26,12 @@ end:
ret i64 %v
}
-; CHECK-LABEL: @foo16
-; CHECK: kmov
-; CHECK: kmov
-; CHECK: orl $65534, %eax
-; CHECK: retq
-define i16 @foo16(i1 zeroext %i, i32 %j) #0 {
+define i16 @foo16(i1 zeroext %i) #0 {
+; CHECK-LABEL: foo16:
+; CHECK: # BB#0:
+; CHECK-NEXT: orl $65534, %edi # imm = 0xFFFE
+; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: retq
br label %bb
bb:
@@ -38,3 +42,68 @@ bb:
end:
ret i16 %v
}
+
+; This code is still not optimal
+define i16 @foo16_1(i1 zeroext %i, i32 %j) #0 {
+; KNL-LABEL: foo16_1:
+; KNL: # BB#0:
+; KNL-NEXT: kmovw %edi, %k0
+; KNL-NEXT: kmovw %k0, %eax
+; KNL-NEXT: andl $1, %eax
+; KNL-NEXT: orl $2, %eax
+; KNL-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; KNL-NEXT: retq
+;
+; SKX-LABEL: foo16_1:
+; SKX: # BB#0:
+; SKX-NEXT: kmovd %edi, %k0
+; SKX-NEXT: kmovw %k0, %eax
+; SKX-NEXT: andl $1, %eax
+; SKX-NEXT: orl $2, %eax
+; SKX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
+; SKX-NEXT: retq
+ br label %bb
+
+bb:
+ %z = zext i1 %i to i16
+ %v = or i16 %z, 2
+ br label %end
+
+end:
+ ret i16 %v
+}
+
+define i32 @foo32(i1 zeroext %i) #0 {
+; CHECK-LABEL: foo32:
+; CHECK: # BB#0:
+; CHECK-NEXT: orl $-2, %edi
+; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: retq
+ br label %bb
+
+bb:
+ %z = zext i1 %i to i32
+ %v = or i32 %z, -2
+ br label %end
+
+end:
+ ret i32 %v
+}
+
+define i8 @foo8(i1 zeroext %i) #0 {
+; CHECK-LABEL: foo8:
+; CHECK: # BB#0:
+; CHECK-NEXT: orb $-2, %dil
+; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: retq
+ br label %bb
+
+bb:
+ %z = zext i1 %i to i8
+ %v = or i8 %z, -2
+ br label %end
+
+end:
+ ret i8 %v
+}
+
diff --git a/llvm/test/CodeGen/X86/xaluo.ll b/llvm/test/CodeGen/X86/xaluo.ll
index 75743b083f3..de20647e0fa 100644
--- a/llvm/test/CodeGen/X86/xaluo.ll
+++ b/llvm/test/CodeGen/X86/xaluo.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=x86_64-darwin-unknown < %s | FileCheck %s --check-prefix=CHECK --check-prefix=SDAG
; RUN: llc -mtriple=x86_64-darwin-unknown -fast-isel -fast-isel-abort=1 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=FAST
; RUN: llc -mtriple=x86_64-darwin-unknown -mcpu=knl < %s | FileCheck %s --check-prefix=KNL
@@ -738,15 +739,15 @@ define i1 @bug27873(i64 %c1, i1 %c2) {
; KNL-LABEL: bug27873:
; KNL: ## BB#0:
; KNL-NEXT: andl $1, %esi
+; KNL-NEXT: kmovw %esi, %k0
; KNL-NEXT: movl $160, %ecx
; KNL-NEXT: movq %rdi, %rax
; KNL-NEXT: mulq %rcx
-; KNL-NEXT: kmovw %esi, %k0
; KNL-NEXT: seto %al
; KNL-NEXT: kmovw %eax, %k1
; KNL-NEXT: korw %k1, %k0, %k0
; KNL-NEXT: kmovw %k0, %eax
-; KNL-NEXT: # kill
+; KNL-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
; KNL-NEXT: retq
%mul = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 %c1, i64 160)
%mul.overflow = extractvalue { i64, i1 } %mul, 1
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