15 files changed, 714 insertions, 22 deletions
diff --git a/llvm/test/CodeGen/Hexagon/intrinsics/v65-gather-double.ll b/llvm/test/CodeGen/Hexagon/intrinsics/v65-gather-double.ll
new file mode 100644
index 00000000000..453f690f89f
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/intrinsics/v65-gather-double.ll
@@ -0,0 +1,60 @@
+; RUN: llc -mv65 -mattr=+hvxv65,hvx-length128b -march=hexagon -O2 < %s | FileCheck %s
+
+; CHECK-LABEL: V6_vgathermw_128B
+; CHECK: vtmp.w = vgather(r1,m{{[0-9]+}},v{{[0-9]+}}.w).w
+; CHECK: vmem(r{{[0-9]+}}+#0) = vtmp.new
+; CHECK-LABEL: V6_vgathermh_128B
+; CHECK: vtmp.h = vgather(r1,m{{[0-9]+}},v{{[0-9]+}}.h).h
+; CHECK: vmem(r{{[0-9]+}}+#0) = vtmp.new
+; CHECK-LABEL: V6_vgathermhw_128B
+; CHECK: vtmp.h = vgather(r1,m{{[0-9]+}},v{{[0-9]+}}:{{[0-9]+}}.w).h
+; CHECK: vmem(r{{[0-9]+}}+#0) = vtmp.new
+; CHECK-LABEL: V6_vgathermwq_128B
+; CHECK: if (q{{[0-3]+}}) vtmp.w = vgather(r1,m{{[0-9]+}},v{{[0-9]+}}.w).w
+; CHECK: vmem(r{{[0-9]+}}+#0) = vtmp.new
+; CHECK-LABEL: V6_vgathermhq_128B
+; CHECK: if (q{{[0-3]+}}) vtmp.h = vgather(r1,m{{[0-9]+}},v{{[0-9]+}}.h).h
+; CHECK: vmem(r{{[0-9]+}}+#0) = vtmp.new
+; CHECK-LABEL: V6_vgathermhwq_128B
+; CHECK: if (q{{[0-3]+}}) vtmp.h = vgather(r1,m{{[0-9]+}},v{{[0-9]+}}:{{[0-9]+}}.w).h
+; CHECK: vmem(r{{[0-9]+}}+#0) = vtmp.new
+
+declare void @llvm.hexagon.V6.vgathermw.128B(i8*, i32, i32, <32 x i32>)
+define void @V6_vgathermw_128B(i8* %a, i32 %b, i32 %c, <32 x i32> %d) {
+  call void @llvm.hexagon.V6.vgathermw.128B(i8* %a, i32 %b, i32 %c, <32 x i32> %d)
+  ret void
+}
+
+declare void @llvm.hexagon.V6.vgathermh.128B(i8*, i32, i32, <32 x i32>)
+define void @V6_vgathermh_128B(i8* %a, i32 %b, i32 %c, <32 x i32> %d) {
+  call void @llvm.hexagon.V6.vgathermh.128B(i8* %a, i32 %b, i32 %c, <32 x i32> %d)
+  ret void
+}
+
+declare void @llvm.hexagon.V6.vgathermhw.128B(i8*, i32, i32, <64 x i32>)
+define void @V6_vgathermhw_128B(i8* %a, i32 %b, i32 %c, <64 x i32> %d) {
+  call void @llvm.hexagon.V6.vgathermhw.128B(i8* %a, i32 %b, i32 %c, <64 x i32> %d)
+  ret void
+}
+
+declare void @llvm.hexagon.V6.vgathermwq.128B(i8*, <1024 x i1>, i32, i32, <32 x i32>)
+define void @V6_vgathermwq_128B(i8* %a, <32 x i32> %b, i32 %c, i32 %d, <32 x i32> %e) {
+  %1 = bitcast <32 x i32> %b to <1024 x i1>
+  call void @llvm.hexagon.V6.vgathermwq.128B(i8* %a, <1024 x i1> %1, i32 %c, i32 %d, <32 x i32> %e)
+  ret void
+}
+
+declare void @llvm.hexagon.V6.vgathermhq.128B(i8*, <1024 x i1>, i32, i32, <32 x i32>)
+define void @V6_vgathermhq_128B(i8* %a, <32 x i32> %b, i32 %c, i32 %d, <32 x i32> %e) {
+  %1 = bitcast <32 x i32> %b to <1024 x i1>
+  call void @llvm.hexagon.V6.vgathermhq.128B(i8* %a, <1024 x i1> %1, i32 %c, i32 %d, <32 x i32> %e)
+  ret void
+}
+
+declare void @llvm.hexagon.V6.vgathermhwq.128B(i8*, <1024 x i1>, i32, i32, <64 x i32>)
+define void @V6_vgathermhwq_128B(i8* %a, <32 x i32> %b, i32 %c, i32 %d, <64 x i32> %e) {
+  %1 = bitcast <32 x i32> %b to <1024 x i1>
+  call void @llvm.hexagon.V6.vgathermhwq.128B(i8* %a, <1024 x i1> %1, i32 %c, i32 %d, <64 x i32> %e)
+  ret void
+}
+
diff --git a/llvm/test/CodeGen/Hexagon/intrinsics/v65-gather.ll b/llvm/test/CodeGen/Hexagon/intrinsics/v65-gather.ll
new file mode 100644
index 00000000000..bc8591527c0
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/intrinsics/v65-gather.ll
@@ -0,0 +1,59 @@
+; RUN: llc -mv65 -mattr=+hvxv65,hvx-length64b -march=hexagon -O2 < %s | FileCheck %s
+
+; CHECK-LABEL: V6_vgathermw
+; CHECK: vtmp.w = vgather(r1,m{{[0-9]+}},v{{[0-9]+}}.w).w
+; CHECK: vmem(r{{[0-9]+}}+#0) = vtmp.new
+; CHECK-LABEL: V6_vgathermh
+; CHECK: vtmp.h = vgather(r1,m{{[0-9]+}},v{{[0-9]+}}.h).h
+; CHECK: vmem(r{{[0-9]+}}+#0) = vtmp.new
+; CHECK-LABEL: V6_vgathermhw
+; CHECK: vtmp.h = vgather(r1,m{{[0-9]+}},v{{[0-9]+}}:{{[0-9]+}}.w).h
+; CHECK: vmem(r{{[0-9]+}}+#0) = vtmp.new
+; CHECK-LABEL: V6_vgathermwq
+; CHECK: if (q{{[0-3]+}}) vtmp.w = vgather(r1,m{{[0-9]+}},v{{[0-9]+}}.w).w
+; CHECK: vmem(r{{[0-9]+}}+#0) = vtmp.new
+; CHECK-LABEL: V6_vgathermhq
+; CHECK: if (q{{[0-3]+}}) vtmp.h = vgather(r1,m{{[0-9]+}},v{{[0-9]+}}.h).h
+; CHECK: vmem(r{{[0-9]+}}+#0) = vtmp.new
+; CHECK-LABEL: V6_vgathermhwq
+; CHECK: if (q{{[0-3]+}}) vtmp.h = vgather(r1,m{{[0-9]+}},v{{[0-9]+}}:{{[0-9]+}}.w).h
+; CHECK: vmem(r{{[0-9]+}}+#0) = vtmp.new
+
+declare void @llvm.hexagon.V6.vgathermw(i8*, i32, i32, <16 x i32>)
+define void @V6_vgathermw(i8* %a, i32 %b, i32 %c, <16 x i32> %d) {
+  call void @llvm.hexagon.V6.vgathermw(i8* %a, i32 %b, i32 %c, <16 x i32> %d)
+  ret void
+}
+
+declare void @llvm.hexagon.V6.vgathermh(i8*, i32, i32, <16 x i32>)
+define void @V6_vgathermh(i8* %a, i32 %b, i32 %c, <16 x i32> %d) {
+  call void @llvm.hexagon.V6.vgathermh(i8* %a, i32 %b, i32 %c, <16 x i32> %d)
+  ret void
+}
+
+declare void @llvm.hexagon.V6.vgathermhw(i8*, i32, i32, <32 x i32>)
+define void @V6_vgathermhw(i8* %a, i32 %b, i32 %c, <32 x i32> %d) {
+  call void @llvm.hexagon.V6.vgathermhw(i8* %a, i32 %b, i32 %c, <32 x i32> %d)
+  ret void
+}
+
+declare void @llvm.hexagon.V6.vgathermwq(i8*, <512 x i1>, i32, i32, <16 x i32>)
+define void @V6_vgathermwq(i8* %a, <16 x i32> %b, i32 %c, i32 %d, <16 x i32> %e) {
+  %1 = bitcast <16 x i32> %b to <512 x i1>
+  call void @llvm.hexagon.V6.vgathermwq(i8* %a, <512 x i1> %1, i32 %c, i32 %d, <16 x i32> %e)
+  ret void
+}
+
+declare void @llvm.hexagon.V6.vgathermhq(i8*, <512 x i1>, i32, i32, <16 x i32>)
+define void @V6_vgathermhq(i8* %a, <16 x i32> %b, i32 %c, i32 %d, <16 x i32> %e) {
+  %1 = bitcast <16 x i32> %b to <512 x i1>
+  call void @llvm.hexagon.V6.vgathermhq(i8* %a, <512 x i1> %1, i32 %c, i32 %d, <16 x i32> %e)
+  ret void
+}
+
+declare void @llvm.hexagon.V6.vgathermhwq(i8*, <512 x i1>, i32, i32, <32 x i32>)
+define void @V6_vgathermhwq(i8* %a, <16 x i32> %b, i32 %c, i32 %d, <32 x i32> %e) {
+  %1 = bitcast <16 x i32> %b to <512 x i1>
+  call void @llvm.hexagon.V6.vgathermhwq(i8* %a, <512 x i1> %1, i32 %c, i32 %d, <32 x i32> %e)
+  ret void
+}
diff --git a/llvm/test/CodeGen/Hexagon/intrinsics/v65-scatter-double.ll b/llvm/test/CodeGen/Hexagon/intrinsics/v65-scatter-double.ll
new file mode 100644
index 00000000000..40366fa3af1
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/intrinsics/v65-scatter-double.ll
@@ -0,0 +1,78 @@
+; RUN: llc -mv65 -mattr=+hvxv65,hvx-length128b -march=hexagon -O2 < %s | FileCheck %s
+
+; CHECK-LABEL: V6_vscattermw_128B
+; CHECK: vscatter(r{{[0-9]+}},m{{[0-9]+}},v{{[0-9]+}}.w).w = v{{[0-9]+}}
+; CHECK-LABEL: V6_vscattermh_128B
+; CHECK: vscatter(r{{[0-9]+}},m{{[0-9]+}},v{{[0-9]+}}.h).h = v{{[0-9]+}}
+; CHECK-LABEL: V6_vscattermw_add_128B
+; CHECK: vscatter(r{{[0-9]+}},m{{[0-9]+}},v{{[0-9]+}}.w).w += v{{[0-9]+}}
+; CHECK-LABEL: V6_vscattermh_add_128B
+; CHECK: vscatter(r{{[0-9]+}},m{{[0-9]+}},v{{[0-9]+}}.h).h += v{{[0-9]+}}
+; CHECK-LABEL: V6_vscattermwq_128B
+; CHECK: if (q{{[0-3]}}) vscatter(r{{[0-9]+}},m{{[0-9]+}},v{{[0-9]+}}.w).w = v{{[0-9]+}}
+; CHECK-LABEL: V6_vscattermhq_128B
+; CHECK: if (q{{[0-3]}}) vscatter(r{{[0-9]+}},m{{[0-9]+}},v{{[0-9]+}}.h).h = v{{[0-9]+}}
+; CHECK-LABEL: V6_vscattermhw_128B
+; CHECK: vscatter(r{{[0-9]+}},m{{[0-9]+}},v{{[0-9]+}}:{{[0-9]+}}.w).h = v{{[0-9]+}}
+; CHECK-LABEL: V6_vscattermhw_add_128B
+; CHECK: vscatter(r{{[0-9]+}},m{{[0-9]+}},v{{[0-9]+}}:{{[0-9]+}}.w).h += v{{[0-9]+}}
+; CHECK-LABEL: V6_vscattermhwq_128B
+; CHECK: if (q{{[0-3]}}) vscatter(r{{[0-9]+}},m{{[0-9]+}},v{{[0-9]+}}:{{[0-9]+}}.w).h = v{{[0-9]+}}
+
+
+declare void @llvm.hexagon.V6.vscattermw.128B(i32, i32, <32 x i32>, <32 x i32>)
+define void @V6_vscattermw_128B(i32 %a, i32 %b, <32 x i32> %c, <32 x i32> %d) {
+  call void @llvm.hexagon.V6.vscattermw.128B(i32 %a, i32 %b, <32 x i32> %c, <32 x i32> %d)
+  ret void
+}
+
+declare void @llvm.hexagon.V6.vscattermh.128B(i32, i32, <32 x i32>, <32 x i32>)
+define void @V6_vscattermh_128B(i32 %a, i32 %b, <32 x i32> %c, <32 x i32> %d) {
+  call void @llvm.hexagon.V6.vscattermh.128B(i32 %a, i32 %b, <32 x i32> %c, <32 x i32> %d)
+  ret void
+}
+
+declare void @llvm.hexagon.V6.vscattermw.add.128B(i32, i32, <32 x i32>, <32 x i32>)
+define void @V6_vscattermw_add_128B(i32 %a, i32 %b, <32 x i32> %c, <32 x i32> %d) {
+  call void @llvm.hexagon.V6.vscattermw.add.128B(i32 %a, i32 %b, <32 x i32> %c, <32 x i32> %d)
+  ret void
+}
+
+declare void @llvm.hexagon.V6.vscattermh.add.128B(i32, i32, <32 x i32>, <32 x i32>)
+define void @V6_vscattermh_add_128B(i32 %a, i32 %b, <32 x i32> %c, <32 x i32> %d) {
+  call void @llvm.hexagon.V6.vscattermh.add.128B(i32 %a, i32 %b, <32 x i32> %c, <32 x i32> %d)
+  ret void
+}
+
+declare void @llvm.hexagon.V6.vscattermwq.128B(<1024 x i1>, i32, i32, <32 x i32>, <32 x i32>)
+define void @V6_vscattermwq_128B(<32 x i32> %a, i32 %b, i32 %c, <32 x i32> %d, <32 x i32> %e) {
+  %1 = bitcast <32 x i32> %a to <1024 x i1>
+  call void @llvm.hexagon.V6.vscattermwq.128B(<1024 x i1> %1, i32 %b, i32 %c, <32 x i32> %d, <32 x i32> %e)
+  ret void
+}
+
+declare void @llvm.hexagon.V6.vscattermhq.128B(<1024 x i1>, i32, i32, <32 x i32>, <32 x i32>)
+define void @V6_vscattermhq_128B(<32 x i32> %a, i32 %b, i32 %c, <32 x i32> %d, <32 x i32> %e) {
+  %1 = bitcast <32 x i32> %a to <1024 x i1>
+  call void @llvm.hexagon.V6.vscattermhq.128B(<1024 x i1> %1, i32 %b, i32 %c, <32 x i32> %d, <32 x i32> %e)
+  ret void
+}
+
+declare void @llvm.hexagon.V6.vscattermhw.128B(i32, i32, <64 x i32>, <32 x i32>)
+define void @V6_vscattermhw_128B(i32 %a, i32 %b, <64 x i32> %c, <32 x i32> %d) {
+  call void @llvm.hexagon.V6.vscattermhw.128B(i32 %a, i32 %b, <64 x i32> %c, <32 x i32> %d)
+  ret void
+}
+
+declare void @llvm.hexagon.V6.vscattermhw.add.128B(i32, i32, <64 x i32>, <32 x i32>)
+define void @V6_vscattermhw_add_128B(i32 %a, i32 %b, <64 x i32> %c, <32 x i32> %d) {
+  call void @llvm.hexagon.V6.vscattermhw.add.128B(i32 %a, i32 %b, <64 x i32> %c, <32 x i32> %d)
+  ret void
+}
+
+declare void @llvm.hexagon.V6.vscattermhwq.128B(<1024 x i1>, i32, i32, <64 x i32>, <32 x i32>)
+define void @V6_vscattermhwq_128B(<32 x i32> %a, i32 %b, i32 %c, <64 x i32> %d, <32 x i32> %e) {
+  %1 = bitcast <32 x i32> %a to <1024 x i1>
+  call void @llvm.hexagon.V6.vscattermhwq.128B(<1024 x i1> %1, i32 %b, i32 %c, <64 x i32> %d, <32 x i32> %e)
+  ret void
+}
diff --git a/llvm/test/CodeGen/Hexagon/intrinsics/v65-scatter-gather.ll b/llvm/test/CodeGen/Hexagon/intrinsics/v65-scatter-gather.ll
new file mode 100644
index 00000000000..2ebd22bdfb4
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/intrinsics/v65-scatter-gather.ll
@@ -0,0 +1,32 @@
+; RUN: llc -mv65 -mattr=+hvxv65,hvx-length64b -march=hexagon -O2 < %s | FileCheck %s
+; RUN: llc -mv65 -mattr=+hvxv65,hvx-length64b -march=hexagon -O2 -disable-packetizer < %s | FileCheck %s
+; RUN: llc -mv65 -mattr=+hvxv65,hvx-length64b -march=hexagon -O0 < %s | FileCheck %s
+
+; CHECK: vtmp.h = vgather(r{{[0-9]+}},m{{[0-9]+}},v{{[0-9]+}}.h).h
+; CHECK-NEXT: vmem(r{{[0-9]+}}+#0) = vtmp.new
+; CHECK-NEXT: }
+
+declare i32 @add_translation_extended(i32, i8*, i64, i32, i32, i32, i32, i32, i32) local_unnamed_addr
+
+; Function Attrs: nounwind
+define i32 @main() local_unnamed_addr {
+entry:
+  %hvx_vector = alloca <16 x i32>, align 64
+  %0 = bitcast <16 x i32>* %hvx_vector to i8*
+  %call.i = tail call i32 @add_translation_extended(i32 1, i8* inttoptr (i32 -668991488 to i8*), i64 3625975808, i32 16, i32 15, i32 0, i32 0, i32 0, i32 3)
+  %1 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 1)
+  %2 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 2)
+  tail call void @llvm.hexagon.V6.vscattermh.add(i32 -668991488, i32 1023, <16 x i32> %1, <16 x i32> %2)
+  call void @llvm.hexagon.V6.vgathermh(i8* %0, i32 -668991488, i32 1023, <16 x i32> %1)
+  ret i32 0
+}
+
+; Function Attrs: nounwind writeonly
+declare void @llvm.hexagon.V6.vscattermh.add(i32, i32, <16 x i32>, <16 x i32>)
+
+; Function Attrs: nounwind readnone
+declare <16 x i32> @llvm.hexagon.V6.lvsplatw(i32)
+
+; Function Attrs: argmemonly nounwind
+declare void @llvm.hexagon.V6.vgathermh(i8*, i32, i32, <16 x i32>)
+
diff --git a/llvm/test/CodeGen/Hexagon/intrinsics/v65-scatter.ll b/llvm/test/CodeGen/Hexagon/intrinsics/v65-scatter.ll
new file mode 100644
index 00000000000..405211c5dfa
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/intrinsics/v65-scatter.ll
@@ -0,0 +1,78 @@
+; RUN: llc -mv65 -mattr=+hvxv65,hvx-length64b -march=hexagon -O2 < %s | FileCheck %s
+
+; CHECK-LABEL: V6_vscattermw
+; CHECK: vscatter(r{{[0-9]+}},m{{[0-9]+}},v{{[0-9]+}}.w).w = v{{[0-9]+}}
+; CHECK-LABEL: V6_vscattermh
+; CHECK: vscatter(r{{[0-9]+}},m{{[0-9]+}},v{{[0-9]+}}.h).h = v{{[0-9]+}}
+; CHECK-LABEL: V6_vscattermw_add
+; CHECK: vscatter(r{{[0-9]+}},m{{[0-9]+}},v{{[0-9]+}}.w).w += v{{[0-9]+}}
+; CHECK-LABEL: V6_vscattermh_add
+; CHECK: vscatter(r{{[0-9]+}},m{{[0-9]+}},v{{[0-9]+}}.h).h += v{{[0-9]+}}
+; CHECK-LABEL: V6_vscattermwq
+; CHECK: if (q{{[0-3]}}) vscatter(r{{[0-9]+}},m{{[0-9]+}},v{{[0-9]+}}.w).w = v{{[0-9]+}}
+; CHECK-LABEL: V6_vscattermhq
+; CHECK: if (q{{[0-3]}}) vscatter(r{{[0-9]+}},m{{[0-9]+}},v{{[0-9]+}}.h).h = v{{[0-9]+}}
+; CHECK-LABEL: V6_vscattermhw
+; CHECK: vscatter(r{{[0-9]+}},m{{[0-9]+}},v{{[0-9]+}}:{{[0-9]+}}.w).h = v{{[0-9]+}}
+; CHECK-LABEL: V6_vscattermhw_add
+; CHECK: vscatter(r{{[0-9]+}},m{{[0-9]+}},v{{[0-9]+}}:{{[0-9]+}}.w).h += v{{[0-9]+}}
+; CHECK-LABEL: V6_vscattermhwq
+; CHECK: if (q{{[0-3]}}) vscatter(r{{[0-9]+}},m{{[0-9]+}},v{{[0-9]+}}:{{[0-9]+}}.w).h = v{{[0-9]+}}
+
+
+declare void @llvm.hexagon.V6.vscattermw(i32, i32, <16 x i32>, <16 x i32>)
+define void @V6_vscattermw(i32 %a, i32 %b, <16 x i32> %c, <16 x i32> %d) {
+  call void @llvm.hexagon.V6.vscattermw(i32 %a, i32 %b, <16 x i32> %c, <16 x i32> %d)
+  ret void
+}
+
+declare void @llvm.hexagon.V6.vscattermh(i32, i32, <16 x i32>, <16 x i32>)
+define void @V6_vscattermh(i32 %a, i32 %b, <16 x i32> %c, <16 x i32> %d) {
+  call void @llvm.hexagon.V6.vscattermh(i32 %a, i32 %b, <16 x i32> %c, <16 x i32> %d)
+  ret void
+}
+
+declare void @llvm.hexagon.V6.vscattermw.add(i32, i32, <16 x i32>, <16 x i32>)
+define void @V6_vscattermw_add(i32 %a, i32 %b, <16 x i32> %c, <16 x i32> %d) {
+  call void @llvm.hexagon.V6.vscattermw.add(i32 %a, i32 %b, <16 x i32> %c, <16 x i32> %d)
+  ret void
+}
+
+declare void @llvm.hexagon.V6.vscattermh.add(i32, i32, <16 x i32>, <16 x i32>)
+define void @V6_vscattermh_add(i32 %a, i32 %b, <16 x i32> %c, <16 x i32> %d) {
+  call void @llvm.hexagon.V6.vscattermh.add(i32 %a, i32 %b, <16 x i32> %c, <16 x i32> %d)
+  ret void
+}
+
+declare void @llvm.hexagon.V6.vscattermwq(<512 x i1>, i32, i32, <16 x i32>, <16 x i32>)
+define void @V6_vscattermwq(<16 x i32> %a, i32 %b, i32 %c, <16 x i32> %d, <16 x i32> %e) {
+  %1 = bitcast <16 x i32> %a to <512 x i1>
+  call void @llvm.hexagon.V6.vscattermwq(<512 x i1> %1, i32 %b, i32 %c, <16 x i32> %d, <16 x i32> %e)
+  ret void
+}
+
+declare void @llvm.hexagon.V6.vscattermhq(<512 x i1>, i32, i32, <16 x i32>, <16 x i32>)
+define void @V6_vscattermhq(<16 x i32> %a, i32 %b, i32 %c, <16 x i32> %d, <16 x i32> %e) {
+  %1 = bitcast <16 x i32> %a to <512 x i1>
+  call void @llvm.hexagon.V6.vscattermhq(<512 x i1> %1, i32 %b, i32 %c, <16 x i32> %d, <16 x i32> %e)
+  ret void
+}
+
+declare void @llvm.hexagon.V6.vscattermhw(i32, i32, <32 x i32>, <16 x i32>)
+define void @V6_vscattermhw(i32 %a, i32 %b, <32 x i32> %c, <16 x i32> %d) {
+  call void @llvm.hexagon.V6.vscattermhw(i32 %a, i32 %b, <32 x i32> %c, <16 x i32> %d)
+  ret void
+}
+
+declare void @llvm.hexagon.V6.vscattermhw.add(i32, i32, <32 x i32>, <16 x i32>)
+define void @V6_vscattermhw_add(i32 %a, i32 %b, <32 x i32> %c, <16 x i32> %d) {
+  call void @llvm.hexagon.V6.vscattermhw.add(i32 %a, i32 %b, <32 x i32> %c, <16 x i32> %d)
+  ret void
+}
+
+declare void @llvm.hexagon.V6.vscattermhwq(<512 x i1>, i32, i32, <32 x i32>, <16 x i32>)
+define void @V6_vscattermhwq(<16 x i32> %a, i32 %b, i32 %c, <32 x i32> %d, <16 x i32> %e) {
+  %1 = bitcast <16 x i32> %a to <512 x i1>
+  call void @llvm.hexagon.V6.vscattermhwq(<512 x i1> %1, i32 %b, i32 %c, <32 x i32> %d, <16 x i32> %e)
+  ret void
+}
diff --git a/llvm/test/CodeGen/Hexagon/intrinsics/v65.ll b/llvm/test/CodeGen/Hexagon/intrinsics/v65.ll
new file mode 100644
index 00000000000..8d503f11800
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/intrinsics/v65.ll
@@ -0,0 +1,156 @@
+; RUN: llc -mv65 -mattr=+hvxv65,hvx-length64b -march=hexagon -O0 < %s | FileCheck %s
+; RUN: llc -mv65 -mattr=+hvxv65,hvx-length64b -march=hexagon -O0 < %s | FileCheck -check-prefix=CHECK-CALL %s
+
+; CHECK-CALL-NOT: call
+
+declare i32 @llvm.hexagon.A6.vcmpbeq.notany(i64, i64)
+define i32 @A6_vcmpbeq_notany(i64 %a, i64 %b) {
+  %c = call i32 @llvm.hexagon.A6.vcmpbeq.notany(i64 %a, i64 %b)
+  ret i32 %c
+}
+; CHECK = !any8(vcmpb.eq(r1:0,r3:2))
+
+declare <16 x i32> @llvm.hexagon.V6.vabsb(<16 x i32>)
+define <16 x i32> @V6_vabsb(<16 x i32> %a) {
+  %b = call <16 x i32> @llvm.hexagon.V6.vabsb(<16 x i32> %a)
+  ret <16 x i32> %b
+}
+; CHECK: = vabs(v0.b)
+
+declare <16 x i32> @llvm.hexagon.V6.vabsb.sat(<16 x i32>)
+define <16 x i32> @V6_vabsb_sat(<16 x i32> %a) {
+  %b = call <16 x i32> @llvm.hexagon.V6.vabsb.sat(<16 x i32> %a)
+  ret <16 x i32> %b
+}
+; CHECK: = vabs(v0.b):sat
+
+declare <16 x i32> @llvm.hexagon.V6.vaslh.acc(<16 x i32>, <16 x i32>, i32)
+define <16 x i32> @V6_vaslh_acc(<16 x i32> %a, <16 x i32> %b, i32 %c) {
+  %d = call <16 x i32> @llvm.hexagon.V6.vaslh.acc(<16 x i32> %a, <16 x i32> %b, i32 %c)
+  ret <16 x i32> %d
+}
+; CHECK: += vasl(v1.h,r0)
+
+declare <16 x i32> @llvm.hexagon.V6.vasrh.acc(<16 x i32>, <16 x i32>, i32)
+define <16 x i32> @V6_vasrh_acc(<16 x i32> %a, <16 x i32> %b, i32 %c) {
+  %d = call <16 x i32> @llvm.hexagon.V6.vasrh.acc(<16 x i32> %a, <16 x i32> %b, i32 %c)
+  ret <16 x i32> %d
+}
+; CHECK: += vasr(v1.h,r0)
+
+declare <16 x i32> @llvm.hexagon.V6.vasruwuhsat(<16 x i32>, <16 x i32>, i32)
+define <16 x i32> @V6_vasruwuhsat(<16 x i32> %a, <16 x i32> %b, i32 %c) {
+  %d = call <16 x i32> @llvm.hexagon.V6.vasruwuhsat(<16 x i32> %a, <16 x i32> %b, i32 %c)
+  ret <16 x i32> %d
+}
+; CHECK: = vasr(v0.uw,v1.uw,r0):sat
+
+declare <16 x i32> @llvm.hexagon.V6.vasruhubsat(<16 x i32>, <16 x i32>, i32)
+define <16 x i32> @V6_vasruhubsat(<16 x i32> %a, <16 x i32> %b, i32 %c) {
+  %d = call <16 x i32> @llvm.hexagon.V6.vasruhubsat(<16 x i32> %a, <16 x i32> %b, i32 %c)
+  ret <16 x i32> %d
+}
+; CHECK: = vasr(v0.uh,v1.uh,r0):sat
+
+declare <16 x i32> @llvm.hexagon.V6.vasruhubrndsat(<16 x i32>, <16 x i32>, i32)
+define <16 x i32> @V6_vasruhubrndsat(<16 x i32> %a, <16 x i32> %b, i32 %c) {
+  %d = call <16 x i32> @llvm.hexagon.V6.vasruhubrndsat(<16 x i32> %a, <16 x i32> %b, i32 %c)
+  ret <16 x i32> %d
+}
+; CHECK: = vasr(v0.uh,v1.uh,r0):rnd:sat
+
+declare <16 x i32> @llvm.hexagon.V6.vavguw(<16 x i32>, <16 x i32>)
+define <16 x i32> @V6_vavguw(<16 x i32> %a, <16 x i32> %b) {
+  %c = call <16 x i32> @llvm.hexagon.V6.vavguw(<16 x i32> %a, <16 x i32> %b)
+  ret <16 x i32> %c
+}
+; CHECK: = vavg(v0.uw,v1.uw)
+
+declare <16 x i32> @llvm.hexagon.V6.vavguwrnd(<16 x i32>, <16 x i32>)
+define <16 x i32> @V6_vavguwrnd(<16 x i32> %a, <16 x i32> %b) {
+  %c = call <16 x i32> @llvm.hexagon.V6.vavguwrnd(<16 x i32> %a, <16 x i32> %b)
+  ret <16 x i32> %c
+}
+; CHECK: = vavg(v0.uw,v1.uw):rnd
+
+declare <16 x i32> @llvm.hexagon.V6.vavgb(<16 x i32>, <16 x i32>)
+define <16 x i32> @V6_vavgb(<16 x i32> %a, <16 x i32> %b) {
+  %c = call <16 x i32> @llvm.hexagon.V6.vavgb(<16 x i32> %a, <16 x i32> %b)
+  ret <16 x i32> %c
+}
+; CHECK: = vavg(v0.b,v1.b)
+
+declare <16 x i32> @llvm.hexagon.V6.vavgbrnd(<16 x i32>, <16 x i32>)
+define <16 x i32> @V6_vavgbrnd(<16 x i32> %a, <16 x i32> %b) {
+  %c = call <16 x i32> @llvm.hexagon.V6.vavgbrnd(<16 x i32> %a, <16 x i32> %b)
+  ret <16 x i32> %c
+}
+; CHECK: = vavg(v0.b,v1.b):rnd
+
+declare <16 x i32> @llvm.hexagon.V6.vnavgb(<16 x i32>, <16 x i32>)
+define <16 x i32> @V6_vnavgb(<16 x i32> %a, <16 x i32> %b) {
+  %c = call <16 x i32> @llvm.hexagon.V6.vnavgb(<16 x i32> %a, <16 x i32> %b)
+  ret <16 x i32> %c
+}
+; CHECK: = vnavg(v0.b,v1.b)
+
+declare <32 x i32> @llvm.hexagon.V6.vmpabuu(<32 x i32>, i32)
+define <32 x i32> @V6_vmpabuu(<32 x i32> %a, i32 %b) {
+  %c = call <32 x i32> @llvm.hexagon.V6.vmpabuu(<32 x i32> %a, i32 %b)
+  ret <32 x i32> %c
+}
+; CHECK: = vmpa(v1:0.ub,r0.ub)
+
+declare <32 x i32> @llvm.hexagon.V6.vmpabuu.acc(<32 x i32>, <32 x i32>, i32)
+define <32 x i32> @V6_vmpabuu_acc(<32 x i32> %a, <32 x i32> %b, i32 %c) {
+  %d = call <32 x i32> @llvm.hexagon.V6.vmpabuu.acc(<32 x i32> %a, <32 x i32> %b, i32 %c)
+  ret <32 x i32> %d
+}
+; CHECK: += vmpa(v3:2.ub,r0.ub)
+
+declare <16 x i32> @llvm.hexagon.V6.vmpauhuhsat(<16 x i32>, <16 x i32>, i64)
+define <16 x i32> @V6_vmpauhuhsat(<16 x i32> %a, <16 x i32> %b, i64 %c) {
+  %d = call <16 x i32> @llvm.hexagon.V6.vmpauhuhsat(<16 x i32> %a, <16 x i32> %b, i64 %c)
+  ret <16 x i32> %d
+}
+; CHECK: = vmpa(v0.h,v1.uh,r1:0.uh):sat
+
+declare <16 x i32> @llvm.hexagon.V6.vmpsuhuhsat(<16 x i32>, <16 x i32>, i64)
+define <16 x i32> @V6_vmpsuhuhsat(<16 x i32> %a, <16 x i32> %b, i64 %c) {
+  %d = call <16 x i32> @llvm.hexagon.V6.vmpsuhuhsat(<16 x i32> %a, <16 x i32> %b, i64 %c)
+  ret <16 x i32> %d
+}
+; CHECK: = vmps(v0.h,v1.uh,r1:0.uh):sat
+
+declare <32 x i32> @llvm.hexagon.V6.vmpyh.acc(<32 x i32>, <16 x i32>, i32)
+define <32 x i32> @V6_vmpyh_acc(<32 x i32> %a, <16 x i32> %b, i32 %c) {
+  %d = call <32 x i32> @llvm.hexagon.V6.vmpyh.acc(<32 x i32> %a, <16 x i32> %b, i32 %c)
+  ret <32 x i32> %d
+}
+; CHECK: += vmpy(v2.h,r0.h)
+
+declare <16 x i32> @llvm.hexagon.V6.vmpyuhe(<16 x i32>, i32)
+define <16 x i32> @V6_vmpyuhe(<16 x i32> %a, i32 %b) {
+  %c = call <16 x i32> @llvm.hexagon.V6.vmpyuhe(<16 x i32> %a, i32 %b)
+  ret <16 x i32> %c
+}
+; CHECK: = vmpye(v0.uh,r0.uh)
+
+;declare <16 x i32> @llvm.hexagon.V6.vprefixqb(<512 x i1>)
+;define <16 x i32> @V6_vprefixqb(<512 x i1> %a) {
+;  %b = call <16 x i32> @llvm.hexagon.V6.vprefixqb(<512 x i1> %a)
+;  ret <16 x i32> %b
+;}
+
+;declare <16 x i32> @llvm.hexagon.V6.vprefixqh(<512 x i1>)
+;define <16 x i32> @V6_vprefixqh(<512 x i1> %a) {
+;  %b = call <16 x i32> @llvm.hexagon.V6.vprefixqh(<512 x i1> %a)
+;  ret <16 x i32> %b
+;}
+
+;declare <16 x i32> @llvm.hexagon.V6.vprefixqw(<512 x i1>)
+;define <16 x i32> @V6_vprefixqw(<512 x i1> %a) {
+;  %b = call <16 x i32> @llvm.hexagon.V6.vprefixqw(<512 x i1> %a)
+;  ret <16 x i32> %b
+;}
+
diff --git a/llvm/test/CodeGen/Hexagon/livephysregs-lane-masks.mir b/llvm/test/CodeGen/Hexagon/livephysregs-lane-masks.mir
index b2e1968bb59..82be6b21d5e 100644
--- a/llvm/test/CodeGen/Hexagon/livephysregs-lane-masks.mir
+++ b/llvm/test/CodeGen/Hexagon/livephysregs-lane-masks.mir
@@ -36,5 +36,5 @@ body: |
   bb.2:
     liveins: %r0
         %d8 = L2_loadrd_io %r29, 8
-        L4_return implicit-def %r29, implicit-def %r30, implicit-def %r31, implicit-def %pc, implicit %r30
+        %d15 = L4_return %r29, implicit-def %r29, implicit-def %pc, implicit %r30, implicit %framekey
 
diff --git a/llvm/test/MC/Hexagon/PacketRules/endloop_branches.s b/llvm/test/MC/Hexagon/PacketRules/endloop_branches.s
index fbaa246c068..46d984189b5 100644
--- a/llvm/test/MC/Hexagon/PacketRules/endloop_branches.s
+++ b/llvm/test/MC/Hexagon/PacketRules/endloop_branches.s
@@ -1,12 +1,17 @@
 # RUN: not llvm-mc -triple=hexagon -filetype=asm %s 2>&1 | FileCheck %s
 
-# Check that a branch in an end-loop packet is caught.
-
 { jump unknown
 }:endloop0
-# CHECK: 5:3: error: packet marked with `:endloop0' cannot contain instructions that modify register
+# CHECK: 4:1: error: Branches cannot be in a packet with hardware loops
 
 { jump unknown
 }:endloop1
+# CHECK: 8:1: error: Branches cannot be in a packet with hardware loops
+
+{ call unknown
+}:endloop0
+# CHECK: 12:1: error: Branches cannot be in a packet with hardware loops
 
-# CHECK: 9:3: error: packet marked with `:endloop1' cannot contain instructions that modify register
+{ dealloc_return
+}:endloop0
+# CHECK: 16:1: error: Branches cannot be in a packet with hardware loops
diff --git a/llvm/test/MC/Hexagon/hvx-double-implies-hvx.s b/llvm/test/MC/Hexagon/hvx-double-implies-hvx.s
new file mode 100644
index 00000000000..8719281067d
--- /dev/null
+++ b/llvm/test/MC/Hexagon/hvx-double-implies-hvx.s
@@ -0,0 +1,4 @@
+# RUN: llvm-mc -filetype=obj -arch=hexagon -mv65 -mattr=+hvxv65,+hvx-length128b %s | llvm-objdump -d -mhvx - | FileCheck %s
+
+# CHECK: vhist
+vhist
diff --git a/llvm/test/MC/Hexagon/new-value-check.s b/llvm/test/MC/Hexagon/new-value-check.s
index 978d6f15148..4c0674d7e2f 100644
--- a/llvm/test/MC/Hexagon/new-value-check.s
+++ b/llvm/test/MC/Hexagon/new-value-check.s
@@ -3,36 +3,33 @@
 # RUN: not llvm-mc -triple=hexagon -relax-nv-checks < %s 2>&1 | \
 # RUN:     FileCheck %s --check-prefix=CHECK-RELAXED
 
-# CHECK-STRICT: :12:1: error: register `R0' used with `.new' but not validly modified in the same packet
-# CHECK-RELAXED: :12:1: error: register `R0' used with `.new' but not validly modified in the same packet
+# CHECK-STRICT: :10:3: note: Register producer has the opposite predicate sense as consumer
+# CHECK-RELAXED: :10:3: note: Register producer has the opposite predicate sense as consumer
 {
   # invalid: r0 definition predicated on the opposite condition
   if (p3) r0 = add(r1, r2)
   if (!p3) memb(r20) = r0.new
 }
 
-# CHECK-STRICT: :20:1: error: register `R0' used with `.new' but not validly modified in the same packet
-# CHECK-RELAXED: :20:1: error: register `R0' used with `.new' but not validly modified in the same packet
-{
-  # invalid: new-value compare-and-jump cannot use floating point value
+# CHECK-STRICT: :18:3: note: FPU instructions cannot be new-value producers for jumps
+# CHECK-RELAXED: :18:3: note: FPU instructions cannot be new-value producers for jumps
+# CHECK-RELAXED: :19:3: error: Instruction does not have a valid new register producer
+{ # invalid: new-value compare-and-jump cannot use floating point value
   r0 = sfadd(r1, r2)
   if (cmp.eq(r0.new, #0)) jump:nt .
 }
 
-# CHECK-STRICT: :29:1: error: register `R0' used with `.new' but not validly modified in the same packet
-# CHECK-RELAXED: :29:1: error: register `R0' used with `.new' but not validly modified in the same packet
+# No errors from this point on with the relaxed checks.
+# CHECK-RELAXED-NOT: error
+
+# CHECK-STRICT: :28:3: note: Register producer is predicated and consumer is unconditional
 {
-  # invalid: definition of r0 should be unconditional (not explicitly docu-
-  # mented)
+  # valid in relaxed, p0 could always be true
   if (p0) r0 = r1
   if (cmp.eq(r0.new, #0)) jump:nt .
 }
 
-
-# No errors from this point on with the relaxed checks.
-# CHECK-RELAXED-NOT: error
-
-# CHECK-STRICT: :41:1: error: register `R0' used with `.new' but not validly modified in the same packet
+# CHECK-STRICT: :36:3: note: Register producer does not use the same predicate register as the consumer
 {
   # valid (relaxed): p2 and p3 cannot be proven to violate the new-value
   # requirements
@@ -40,7 +37,7 @@
   if (p2) memb(r20) = r0.new
 }
 
-# CHECK-STRICT: :48:1: error: register `R0' used with `.new' but not validly modified in the same packet
+# CHECK-STRICT: :43:3: note: Register producer is predicated and consumer is unconditional
 {
   # valid (relaxed): p3 could be always true
   if (p3) r0 = add(r1, r2)
diff --git a/llvm/test/MC/Hexagon/v60-misc.s b/llvm/test/MC/Hexagon/v60-misc.s
index 53872d64dcf..a7ec36cfa95 100644
--- a/llvm/test/MC/Hexagon/v60-misc.s
+++ b/llvm/test/MC/Hexagon/v60-misc.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv60 -mattr=+hvx -filetype=obj %s | llvm-objdump -arch=hexagon -mcpu=hexagonv60 -mhvx -d - | FileCheck %s
+# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv60 -mhvx -filetype=obj %s | llvm-objdump -arch=hexagon -mcpu=hexagonv60 -mhvx -d - | FileCheck %s
 
 .L0:
 
diff --git a/llvm/test/MC/Hexagon/v65_all.s b/llvm/test/MC/Hexagon/v65_all.s
new file mode 100644
index 00000000000..4f52a063a34
--- /dev/null
+++ b/llvm/test/MC/Hexagon/v65_all.s
@@ -0,0 +1,184 @@
+# RUN: llvm-mc -arch=hexagon -mv65 -mhvx -filetype=obj %s | llvm-objdump -mv65 -mhvx -d - | FileCheck %s
+
+// Warning: This file is auto generated by mktest.py.  Do not edit!
+// Created on:  2016-06-01 @ 17:33:01
+// Created using:
+//   /usr2/mlambert/Tags/iset.py.v65_20160513
+
+
+//   V6_vmpyuhe_acc
+//   Vx32.uw+=vmpye(Vu32.uh,Rt32.uh)
+     V0.uw+=vmpye(V0.uh,R0.uh)
+# CHECK: 1980e060 { v0.uw += vmpye(v0.uh,r0.uh) }
+
+//   V6_vgathermwq
+//   if (Qs4) vtmp.w=vgather(Rt32,Mu2,Vv32.w).w
+     if (Q0) vtmp.w=vgather(R0,M0,V0.w).w
+# CHECK: 2f00c400 { if (q0) vtmp.w = vgather(r0,m0,v0.w).w }
+
+//   V6_vscattermw
+//   vscatter(Rt32,Mu2,Vv32.w).w=Vw32
+     vscatter(R0,M0,V0.w).w=V0
+# CHECK: 2f20c000 { vscatter(r0,m0,v0.w).w = v0 }
+
+//   V6_vscattermh
+//   vscatter(Rt32,Mu2,Vv32.h).h=Vw32
+     vscatter(R0,M0,V0.h).h=V0
+# CHECK: 2f20c020 { vscatter(r0,m0,v0.h).h = v0 }
+
+//   V6_vlut4
+//   Vd32.h=vlut4(Vu32.uh,Rtt32.h)
+     V0.h=vlut4(V0.uh,R1:0.h)
+# CHECK: 1960c080 { v0.h = vlut4(v0.uh,r1:0.h) }
+
+//   V6_vgathermhwq
+//   if (Qs4) vtmp.h=vgather(Rt32,Mu2,Vvv32.w).h
+     if (Q0) vtmp.h=vgather(R0,M0,V1:0.w).h
+# CHECK: 2f00c600 { if (q0) vtmp.h = vgather(r0,m0,v1:0.w).h }
+
+//   V6_vS32b_srls_ai
+//   vmem(Rt32+#s4):scatter_release
+     vmem(R0+#0):scatter_release
+# CHECK: 2820c028 { vmem(r0+#0):scatter_release }
+
+//   V6_vgathermh
+//   vtmp.h=vgather(Rt32,Mu2,Vv32.h).h
+     vtmp.h=vgather(R0,M0,V0.h).h
+# CHECK: 2f00c100 { vtmp.h = vgather(r0,m0,v0.h).h }
+
+//   V6_vscattermhw
+//   vscatter(Rt32,Mu2,Vvv32.w).h=Vw32
+     vscatter(R0,M0,V1:0.w).h=V0
+# CHECK: 2f20c040 { vscatter(r0,m0,v1:0.w).h = v0 }
+
+//   V6_vS32b_srls_ppu
+//   vmem(Rx32++Mu2):scatter_release
+     vmem(R0++M0):scatter_release
+# CHECK: 2b20c028 { vmem(r0++m0):scatter_release }
+
+//   V6_vscattermhw_add
+//   vscatter(Rt32,Mu2,Vvv32.w).h+=Vw32
+     vscatter(R0,M0,V1:0.w).h+=V0
+# CHECK: 2f20c0c0 { vscatter(r0,m0,v1:0.w).h += v0 }
+
+//   V6_vmpabuu
+//   Vdd32.h=vmpa(Vuu32.ub,Rt32.ub)
+     V1:0.h=vmpa(V1:0.ub,R0.ub)
+# CHECK: 1960c060 { v1:0.h = vmpa(v1:0.ub,r0.ub) }
+
+//   V6_vasruhubrndsat
+//   Vd32.ub=vasr(Vu32.uh,Vv32.uh,Rt8):rnd:sat
+     V0.ub=vasr(V0.uh,V0.uh,R0):rnd:sat
+# CHECK: 1800c0e0 { v0.ub = vasr(v0.uh,v0.uh,r0):rnd:sat }
+
+//   V6_vscattermh_add
+//   vscatter(Rt32,Mu2,Vv32.h).h+=Vw32
+     vscatter(R0,M0,V0.h).h+=V0
+# CHECK: 2f20c0a0 { vscatter(r0,m0,v0.h).h += v0 }
+
+//   V6_vgathermw
+//   vtmp.w=vgather(Rt32,Mu2,Vv32.w).w
+     vtmp.w=vgather(R0,M0,V0.w).w
+# CHECK: 2f00c000 { vtmp.w = vgather(r0,m0,v0.w).w }
+
+//   V6_vasruhubsat
+//   Vd32.ub=vasr(Vu32.uh,Vv32.uh,Rt8):sat
+     V0.ub=vasr(V0.uh,V0.uh,R0):sat
+# CHECK: 1800e0a0 { v0.ub = vasr(v0.uh,v0.uh,r0):sat }
+
+//   V6_vscattermhwq
+//   if (Qs4) vscatter(Rt32,Mu2,Vvv32.w).h=Vw32
+     if (Q0) vscatter(R0,M0,V1:0.w).h=V0
+# CHECK: 2fa0c000 { if (q0) vscatter(r0,m0,v1:0.w).h = v0 }
+
+//   V6_vgathermhq
+//   if (Qs4) vtmp.h=vgather(Rt32,Mu2,Vv32.h).h
+     if (Q0) vtmp.h=vgather(R0,M0,V0.h).h
+# CHECK: 2f00c500 { if (q0) vtmp.h = vgather(r0,m0,v0.h).h }
+
+//   V6_vmpsuhuhsat
+//   Vx32.h=vmps(Vx32.h,Vu32.uh,Rtt32.uh):sat
+     V0.h=vmps(V0.h,V0.uh,R1:0.uh):sat
+# CHECK: 1980e0c0 { v0.h = vmps(v0.h,v0.uh,r1:0.uh):sat }
+
+//   V6_vS32b_srls_pi
+//   vmem(Rx32++#s3):scatter_release
+     vmem(R0++#0):scatter_release
+# CHECK: 2920c028 { vmem(r0++#0):scatter_release }
+
+//   V6_vgathermhw
+//   vtmp.h=vgather(Rt32,Mu2,Vvv32.w).h
+     vtmp.h=vgather(R0,M0,V1:0.w).h
+# CHECK: 2f00c200 { vtmp.h = vgather(r0,m0,v1:0.w).h }
+
+//   V6_vmpyuhe
+//   Vd32.uw=vmpye(Vu32.uh,Rt32.uh)
+     V0.uw=vmpye(V0.uh,R0.uh)
+# CHECK: 1960c040 { v0.uw = vmpye(v0.uh,r0.uh) }
+
+//   V6_vscattermwq
+//   if (Qs4) vscatter(Rt32,Mu2,Vv32.w).w=Vw32
+     if (Q0) vscatter(R0,M0,V0.w).w=V0
+# CHECK: 2f80c000 { if (q0) vscatter(r0,m0,v0.w).w = v0 }
+
+//   V6_vasruwuhsat
+//   Vd32.uh=vasr(Vu32.uw,Vv32.uw,Rt8):sat
+     V0.uh=vasr(V0.uw,V0.uw,R0):sat
+# CHECK: 1800e080 { v0.uh = vasr(v0.uw,v0.uw,r0):sat }
+
+//   V6_vprefixqh
+//   Vd32.h=prefixsum(Qv4)
+     V0.h=prefixsum(Q0)
+# CHECK: 1e03e140 { v0.h = prefixsum(q0) }
+
+//   V6_vmpabuu_acc
+//   Vxx32.h+=vmpa(Vuu32.ub,Rt32.ub)
+     V1:0.h+=vmpa(V1:0.ub,R0.ub)
+# CHECK: 19a0e080 { v1:0.h += vmpa(v1:0.ub,r0.ub) }
+
+//   V6_vprefixqw
+//   Vd32.w=prefixsum(Qv4)
+     V0.w=prefixsum(Q0)
+# CHECK: 1e03e240 { v0.w = prefixsum(q0) }
+
+//   V6_vprefixqb
+//   Vd32.b=prefixsum(Qv4)
+     V0.b=prefixsum(Q0)
+# CHECK: 1e03e040 { v0.b = prefixsum(q0) }
+
+//   V6_vabsb
+//   Vd32.b=vabs(Vu32.b)
+     V0.b=vabs(V0.b)
+# CHECK: 1e01c080 { v0.b = vabs(v0.b) }
+
+//   V6_vscattermw_add
+//   vscatter(Rt32,Mu2,Vv32.w).w+=Vw32
+     vscatter(R0,M0,V0.w).w+=V0
+# CHECK: 2f20c080 { vscatter(r0,m0,v0.w).w += v0 }
+
+//   V6_vscattermhq
+//   if (Qs4) vscatter(Rt32,Mu2,Vv32.h).h=Vw32
+     if (Q0) vscatter(R0,M0,V0.h).h=V0
+# CHECK: 2f80c080 { if (q0) vscatter(r0,m0,v0.h).h = v0 }
+
+//   V6_vmpauhuhsat
+//   Vx32.h=vmpa(Vx32.h,Vu32.uh,Rtt32.uh):sat
+     V0.h=vmpa(V0.h,V0.uh,R1:0.uh):sat
+# CHECK: 1980e0a0 { v0.h = vmpa(v0.h,v0.uh,r1:0.uh):sat }
+
+//   V6_vabsb_sat
+//   Vd32.b=vabs(Vu32.b):sat
+     V0.b=vabs(V0.b):sat
+# CHECK: 1e01c0a0 { v0.b = vabs(v0.b):sat }
+
+v1:0.w+=vrmpy(v0.b, r1:0.ub)
+# CHECK: 19a0e000 { v1:0.w += vrmpy(v0.b,r1:0.ub) }
+
+V1:0.uw+=vrmpy(v0.ub,r1:0.ub)
+# CHECK: 19a0e0e0 { v1:0.uw += vrmpy(v0.ub,r1:0.ub) }
+
+v1:0.uw=vrmpy(v1.ub,r1:0.ub)
+# CHECK: 19c0c180 { v1:0.uw = vrmpy(v1.ub,r1:0.ub) }
+
+v1:0.w=vrmpy(v1.b,r1:0.ub)
+# CHECK: 19c0c1a0 { v1:0.w = vrmpy(v1.b,r1:0.ub) }
diff --git a/llvm/test/MC/Hexagon/vpred_defs.s b/llvm/test/MC/Hexagon/vpred_defs.s
new file mode 100644
index 00000000000..92c15a3e575
--- /dev/null
+++ b/llvm/test/MC/Hexagon/vpred_defs.s
@@ -0,0 +1,9 @@
+# RUN: llvm-mc -arch=hexagon -mv65 -filetype=asm -mhvx %s | FileCheck %s
+
+# CHECK-NOT: error: register `{{.+}}' modified more than once
+
+{ Q0 = VCMP.EQ(V0.h,V4.h)
+  Q1 = VCMP.EQ(V1.h,V6.h)
+  IF (Q3) VTMP.h = VGATHER(R0,M0,V3.h).h
+  VMEM(R4++#1) = VTMP.new
+}
diff --git a/llvm/test/MC/Hexagon/vscatter-slot.s b/llvm/test/MC/Hexagon/vscatter-slot.s
new file mode 100644
index 00000000000..6c806de2f98
--- /dev/null
+++ b/llvm/test/MC/Hexagon/vscatter-slot.s
@@ -0,0 +1,25 @@
+# RUN: llvm-mc -arch=hexagon -mv65 -mhvx -filetype=asm < %s | FileCheck %s
+
+# Test that a slot error is not reported for a packet with a load and a
+# vscatter.
+
+# CHECK: vscatter(r0,m0,v0.h).h = v1
+{
+  v1=vmem(r1+#0)
+  vscatter(r0,m0,v0.h).h=v1
+}
+# CHECK: vscatter(r2,m0,v1:0.w).h += v2
+{
+  v1=vmem(r3+#0)
+  vscatter(r2,m0,v1:0.w).h+=v2
+}
+# CHECK: vmem(r4+#0):scatter_release
+{
+  v1=vmem(r5+#0)
+  vmem(r4+#0):scatter_release
+}
+# CHECK: vmem(r4+#0):scatter_release
+{
+  v1=vmem(r5+#0)
+  vmem(r4+#0):scatter_release
+}
diff --git a/llvm/test/MC/Hexagon/vtmp_def.s b/llvm/test/MC/Hexagon/vtmp_def.s
new file mode 100644
index 00000000000..26d257efadd
--- /dev/null
+++ b/llvm/test/MC/Hexagon/vtmp_def.s
@@ -0,0 +1,5 @@
+# RUN: not llvm-mc -arch=hexagon -mv65 -mhvx -filetype=obj %s 2>&1 | FileCheck %s
+
+# CHECK: register `VTMP' modified more than once
+{ vtmp.h=vgather(r0, m0, v1:0.w).h
+  vtmp.h=vgather(r0, m0, v1:0.w).h }