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-rw-r--r--llvm/test/CodeGen/ARM/intrinsics-overflow.ll88
-rw-r--r--llvm/test/CodeGen/ARM/pr34045-2.ll25
-rw-r--r--llvm/test/CodeGen/ARM/pr34045.ll53
3 files changed, 15 insertions, 151 deletions
diff --git a/llvm/test/CodeGen/ARM/intrinsics-overflow.ll b/llvm/test/CodeGen/ARM/intrinsics-overflow.ll
index af555d2240c..af3dd9dd411 100644
--- a/llvm/test/CodeGen/ARM/intrinsics-overflow.ll
+++ b/llvm/test/CodeGen/ARM/intrinsics-overflow.ll
@@ -1,6 +1,4 @@
-; RUN: llc < %s -mtriple=arm-linux -mcpu=generic -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix=ARM
-; RUN: llc < %s -mtriple=thumbv6m-eabi -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix=THUMBV6
-; RUN: llc < %s -mtriple=thumbv7-eabi -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix=THUMBV7
+; RUN: llc < %s -mtriple=arm-linux -mcpu=generic | FileCheck %s
define i32 @uadd_overflow(i32 %a, i32 %b) #0 {
%sadd = tail call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 %a, i32 %b)
@@ -9,19 +7,10 @@ define i32 @uadd_overflow(i32 %a, i32 %b) #0 {
ret i32 %2
; CHECK-LABEL: uadd_overflow:
-
- ; ARM: adds r[[R0:[0-9]+]], r[[R0]], r[[R1:[0-9]+]]
- ; ARM: mov r[[R2:[0-9]+]], #0
- ; ARM: adc r[[R0]], r[[R2]], #0
-
- ; THUMBV6: movs r[[R2:[0-9]+]], #0
- ; THUMBV6: adds r[[R0:[0-9]+]], r[[R0]], r[[R1:[0-9]+]]
- ; THUMBV6: adcs r[[R2]], r[[R2]]
- ; THUMBV6: mov r[[R0]], r[[R2]]
-
- ; THUMBV7: adds r[[R0:[0-9]+]], r[[R0]], r[[R1:[0-9]+]]
- ; THUMBV7: mov.w r[[R2:[0-9]+]], #0
- ; THUMBV7: adc r[[R0]], r[[R2]], #0
+ ; CHECK: add r[[R2:[0-9]+]], r[[R0:[0-9]+]], r[[R1:[0-9]+]]
+ ; CHECK: mov r[[R1]], #1
+ ; CHECK: cmp r[[R2]], r[[R0]]
+ ; CHECK: movhs r[[R1]], #0
}
@@ -32,26 +21,10 @@ define i32 @sadd_overflow(i32 %a, i32 %b) #0 {
ret i32 %2
; CHECK-LABEL: sadd_overflow:
-
- ; ARM: add r[[R2:[0-9]+]], r[[R0:[0-9]+]], r[[R1:[0-9]+]]
- ; ARM: mov r[[R1]], #1
- ; ARM: cmp r[[R2]], r[[R0]]
- ; ARM: movvc r[[R1]], #0
-
- ; THUMBV6: mov r[[R2:[0-9]+]], r[[R0:[0-9]+]]
- ; THUMBV6: adds r[[R3:[0-9]+]], r[[R2]], r[[R1:[0-9]+]]
- ; THUMBV6: movs r[[R0]], #0
- ; THUMBV6: movs r[[R1]], #1
- ; THUMBV6: cmp r[[R3]], r[[R2]]
- ; THUMBV6: bvc .L[[LABEL:.*]]
- ; THUMBV6: mov r[[R0]], r[[R1]]
- ; THUMBV6: .L[[LABEL]]:
-
- ; THUMBV7: movs r[[R1]], #1
- ; THUMBV7: cmp r[[R2]], r[[R0]]
- ; THUMBV7: it vc
- ; THUMBV7: movvc r[[R1]], #0
- ; THUMBV7: mov r[[R0]], r[[R1]]
+ ; CHECK: add r[[R2:[0-9]+]], r[[R0:[0-9]+]], r[[R1:[0-9]+]]
+ ; CHECK: mov r[[R1]], #1
+ ; CHECK: cmp r[[R2]], r[[R0]]
+ ; CHECK: movvc r[[R1]], #0
}
define i32 @usub_overflow(i32 %a, i32 %b) #0 {
@@ -61,26 +34,9 @@ define i32 @usub_overflow(i32 %a, i32 %b) #0 {
ret i32 %2
; CHECK-LABEL: usub_overflow:
-
- ; ARM: subs r[[R0:[0-9]+]], r[[R0]], r[[R1:[0-9]+]]
- ; ARM: mov r[[R2:[0-9]+]], #0
- ; ARM: adc r[[R0]], r[[R2]], #0
- ; ARM: rsb r[[R0]], r[[R0]], #1
-
- ; THUMBV6: movs r[[R2:[0-9]+]], #0
- ; THUMBV6: subs r[[R0:[0-9]+]], r[[R0]], r[[R1:[0-9]+]]
- ; THUMBV6: adcs r[[R2]], r[[R2]]
- ; THUMBV6: movs r[[R0]], #1
- ; THUMBV6: subs r[[R0]], r[[R0]], r[[R2]]
-
- ; THUMBV7: subs r[[R0:[0-9]+]], r[[R0]], r[[R1:[0-9]+]]
- ; THUMBV7: mov.w r[[R2:[0-9]+]], #0
- ; THUMBV7: adc r[[R0]], r[[R2]], #0
- ; THUMBV7: rsb.w r[[R0]], r[[R0]], #1
-
- ; We should know that the overflow is just 1 bit,
- ; no need to clear any other bit
- ; CHECK-NOT: and
+ ; CHECK: mov r[[R2]], #1
+ ; CHECK: cmp r[[R0]], r[[R1]]
+ ; CHECK: movhs r[[R2]], #0
}
define i32 @ssub_overflow(i32 %a, i32 %b) #0 {
@@ -90,23 +46,9 @@ define i32 @ssub_overflow(i32 %a, i32 %b) #0 {
ret i32 %2
; CHECK-LABEL: ssub_overflow:
-
- ; ARM: mov r[[R2]], #1
- ; ARM: cmp r[[R0]], r[[R1]]
- ; ARM: movvc r[[R2]], #0
-
- ; THUMBV6: movs r[[R0]], #0
- ; THUMBV6: movs r[[R3:[0-9]+]], #1
- ; THUMBV6: cmp r[[R2]], r[[R1:[0-9]+]]
- ; THUMBV6: bvc .L[[LABEL:.*]]
- ; THUMBV6: mov r[[R0]], r[[R3]]
- ; THUMBV6: .L[[LABEL]]:
-
- ; THUMBV7: movs r[[R2:[0-9]+]], #1
- ; THUMBV7: cmp r[[R0:[0-9]+]], r[[R1:[0-9]+]]
- ; THUMBV7: it vc
- ; THUMBV7: movvc r[[R2]], #0
- ; THUMBV7: mov r[[R0]], r[[R2]]
+ ; CHECK: mov r[[R2]], #1
+ ; CHECK: cmp r[[R0]], r[[R1]]
+ ; CHECK: movvc r[[R2]], #0
}
declare { i32, i1 } @llvm.uadd.with.overflow.i32(i32, i32) #1
diff --git a/llvm/test/CodeGen/ARM/pr34045-2.ll b/llvm/test/CodeGen/ARM/pr34045-2.ll
deleted file mode 100644
index 94bc3ea3e4f..00000000000
--- a/llvm/test/CodeGen/ARM/pr34045-2.ll
+++ /dev/null
@@ -1,25 +0,0 @@
-; RUN: llc < %s -mtriple thumbv7 | FileCheck %s
-
-define hidden void @foo(i32* %ptr, i1 zeroext %long_blocks) {
-entry:
-; This test is actually checking that no cycle is introduced but at least we
-; want to see one umull.
-; CHECK: umull
- %0 = load i32, i32* %ptr, align 4
- %conv.i.i13.i = zext i32 %0 to i64
- %mul.i.i14.i = mul nuw nsw i64 %conv.i.i13.i, 18782
- %1 = load i32, i32* undef, align 4
- %conv4.i.i16.i = zext i32 %1 to i64
- %add5.i.i17.i = add nuw nsw i64 %mul.i.i14.i, %conv4.i.i16.i
- %shr.i.i18.i = lshr i64 %add5.i.i17.i, 32
- %add10.i.i20.i = add nuw nsw i64 %shr.i.i18.i, %add5.i.i17.i
- %conv11.i.i21.i = trunc i64 %add10.i.i20.i to i32
- %x.0.neg.i.i26.i = sub i32 -2, %conv11.i.i21.i
- %sub.i.i27.i = add i32 %x.0.neg.i.i26.i, 0
- store i32 %sub.i.i27.i, i32* %ptr, align 4
- br label %while.body.i
-
-while.body.i: ; preds = %while.body.i, %entry
- br label %while.body.i
-}
-
diff --git a/llvm/test/CodeGen/ARM/pr34045.ll b/llvm/test/CodeGen/ARM/pr34045.ll
deleted file mode 100644
index 5d52bfe591b..00000000000
--- a/llvm/test/CodeGen/ARM/pr34045.ll
+++ /dev/null
@@ -1,53 +0,0 @@
-; RUN: llc < %s -mtriple thumbv7 | FileCheck %s
-
-; ModuleID = 'bugpoint-reduced-simplified.bc'
-define hidden void @bn_mul_comba8(i32* nocapture %r, i32* nocapture readonly %a, i32* nocapture readonly %b) local_unnamed_addr {
-entry:
-; This test is actually checking that no cycle is introduced but at least we
-; want to see a couple of umull and one umlal in the output
-; CHECK: umull
-; CHECK: umull
-; CHECK: umlal
- %0 = load i32, i32* %a, align 4
- %conv = zext i32 %0 to i64
- %1 = load i32, i32* %b, align 4
- %conv2 = zext i32 %1 to i64
- %mul = mul nuw i64 %conv2, %conv
- %shr = lshr i64 %mul, 32
- %2 = load i32, i32* %a, align 4
- %conv13 = zext i32 %2 to i64
- %3 = load i32, i32* undef, align 4
- %conv15 = zext i32 %3 to i64
- %mul16 = mul nuw i64 %conv15, %conv13
- %add18 = add i64 %mul16, %shr
- %shr20 = lshr i64 %add18, 32
- %conv21 = trunc i64 %shr20 to i32
- %4 = load i32, i32* undef, align 4
- %conv34 = zext i32 %4 to i64
- %5 = load i32, i32* %b, align 4
- %conv36 = zext i32 %5 to i64
- %mul37 = mul nuw i64 %conv36, %conv34
- %conv38 = and i64 %add18, 4294967295
- %add39 = add i64 %mul37, %conv38
- %shr41 = lshr i64 %add39, 32
- %conv42 = trunc i64 %shr41 to i32
- %add43 = add i32 %conv42, %conv21
- %cmp44 = icmp ult i32 %add43, %conv42
- %c1.1 = zext i1 %cmp44 to i32
- %add65 = add i32 0, %c1.1
- %add86 = add i32 %add65, 0
- %add107 = add i32 %add86, 0
- %conv124 = zext i32 %add107 to i64
- %add125 = add i64 0, %conv124
- %conv145 = and i64 %add125, 4294967295
- %add146 = add i64 %conv145, 0
- %conv166 = and i64 %add146, 4294967295
- %add167 = add i64 %conv166, 0
- %conv187 = and i64 %add167, 4294967295
- %add188 = add i64 %conv187, 0
- %conv189 = trunc i64 %add188 to i32
- %arrayidx200 = getelementptr inbounds i32, i32* %r, i32 3
- store i32 %conv189, i32* %arrayidx200, align 4
- ret void
-}
-
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