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-rw-r--r--llvm/test/MC/AArch64/arm32-elf-relocs.s245
-rw-r--r--llvm/test/MC/AArch64/arm64-elf-relocs.s142
-rw-r--r--llvm/test/MC/AArch64/arm64-ilp32.s37
-rw-r--r--llvm/test/MC/AArch64/ilp32-diagnostics.s67
-rw-r--r--llvm/test/tools/llvm-readobj/Inputs/relocs.obj.elf-aarch64-ilp320
-rw-r--r--llvm/test/tools/llvm-readobj/Inputs/relocs.py91
6 files changed, 512 insertions, 70 deletions
diff --git a/llvm/test/MC/AArch64/arm32-elf-relocs.s b/llvm/test/MC/AArch64/arm32-elf-relocs.s
new file mode 100644
index 00000000000..28327164de5
--- /dev/null
+++ b/llvm/test/MC/AArch64/arm32-elf-relocs.s
@@ -0,0 +1,245 @@
+// RUN: llvm-mc -triple=arm64-linux-gnu -o - < %s | FileCheck %s
+// RUN: llvm-mc -target-abi=ilp32 -triple=arm64-linux-gnu -filetype=obj < %s | \
+// RUN: llvm-objdump -triple=arm64-linux-gnu - -r | \
+// RUN: FileCheck %s --check-prefix=CHECK-OBJ-ILP32
+
+ add x0, x2, #:lo12:sym
+// CHECK: add x0, x2, :lo12:sym
+// CHECK-OBJ-ILP32: 0 R_AARCH64_P32_ADD_ABS_LO12_NC sym
+
+ add x5, x7, #:dtprel_lo12:sym
+// CHECK: add x5, x7, :dtprel_lo12:sym
+// CHECK-OBJ-ILP32: 4 R_AARCH64_P32_TLSLD_ADD_DTPREL_LO12 sym
+
+ add x9, x12, #:dtprel_lo12_nc:sym
+// CHECK: add x9, x12, :dtprel_lo12_nc:sym
+// CHECK-OBJ-ILP32: 8 R_AARCH64_P32_TLSLD_ADD_DTPREL_LO12_NC sym
+
+ add x20, x30, #:tprel_lo12:sym
+// CHECK: add x20, x30, :tprel_lo12:sym
+// CHECK-OBJ-ILP32: c R_AARCH64_P32_TLSLE_ADD_TPREL_LO12 sym
+
+ add x9, x12, #:tprel_lo12_nc:sym
+// CHECK: add x9, x12, :tprel_lo12_nc:sym
+// CHECK-OBJ-ILP32: 10 R_AARCH64_P32_TLSLE_ADD_TPREL_LO12_NC sym
+
+ add x5, x0, #:tlsdesc_lo12:sym
+// CHECK: add x5, x0, :tlsdesc_lo12:sym
+// CHECK-OBJ-ILP32: 14 R_AARCH64_P32_TLSDESC_ADD_LO12_NC sym
+
+ add x0, x2, #:lo12:sym+8
+// CHECK: add x0, x2, :lo12:sym
+// CHECK-OBJ-ILP32: 18 R_AARCH64_P32_ADD_ABS_LO12_NC sym+8
+
+ add x5, x7, #:dtprel_lo12:sym+1
+// CHECK: add x5, x7, :dtprel_lo12:sym+1
+// CHECK-OBJ-ILP32: 1c R_AARCH64_P32_TLSLD_ADD_DTPREL_LO12 sym+1
+
+ add x9, x12, #:dtprel_lo12_nc:sym+2
+// CHECK: add x9, x12, :dtprel_lo12_nc:sym+2
+// CHECK-OBJ-ILP32:20 R_AARCH64_P32_TLSLD_ADD_DTPREL_LO12_NC sym+2
+
+ add x20, x30, #:tprel_lo12:sym+12
+// CHECK: add x20, x30, :tprel_lo12:sym+12
+// CHECK-OBJ-ILP32: 24 R_AARCH64_P32_TLSLE_ADD_TPREL_LO12 sym+12
+
+ add x9, x12, #:tprel_lo12_nc:sym+54
+// CHECK: add x9, x12, :tprel_lo12_nc:sym+54
+// CHECK-OBJ-ILP32: 28 R_AARCH64_P32_TLSLE_ADD_TPREL_LO12_NC sym+54
+
+ add x5, x0, #:tlsdesc_lo12:sym+70
+// CHECK: add x5, x0, :tlsdesc_lo12:sym+70
+// CHECK-OBJ-ILP32: 2c R_AARCH64_P32_TLSDESC_ADD_LO12_NC sym+70
+
+ .hword sym + 4 - .
+// CHECK-OBJ-ILP32: 30 R_AARCH64_P32_PREL16 sym+4
+ .word sym - . + 8
+// CHECK-OBJ-ILP32 32 R_AARCH64_P32_PREL32 sym+8
+
+ .hword sym
+// CHECK-OBJ-ILP32 3e R_AARCH64_P32_ABS16 sym
+ .word sym+1
+// CHECK-OBJ-ILP32 40 R_AARCH64_P32_ABS32 sym+1
+
+ adrp x0, sym
+// CHECK: adrp x0, sym
+// CHECK-OBJ-ILP32 4c R_AARCH64_P32_ADR_PREL_PG_HI21 sym
+
+ adrp x15, :got:sym
+// CHECK: adrp x15, :got:sym
+// CHECK-OBJ-ILP32 50 R_AARCH64_P32_ADR_GOT_PAGE sym
+
+ adrp x29, :gottprel:sym
+// CHECK: adrp x29, :gottprel:sym
+// CHECK-OBJ-ILP32 54 R_AARCH64_P32_TLSIE_ADR_GOTTPREL_PAGE21 sym
+
+ adrp x2, :tlsdesc:sym
+// CHECK: adrp x2, :tlsdesc:sym
+// CHECK-OBJ-ILP32 58 R_AARCH64_P32_TLSDESC_ADR_PAGE21 sym
+
+ // LLVM is not competent enough to do this relocation because the
+ // page boundary could occur anywhere after linking. A relocation
+ // is needed.
+ adrp x3, trickQuestion
+ .global trickQuestion
+trickQuestion:
+// CHECK: adrp x3, trickQuestion
+// CHECK-OBJ-ILP32 5c R_AARCH64_P32_ADR_PREL_PG_HI21 trickQuestion
+
+ ldrb w2, [x3, :lo12:sym]
+ ldrsb w5, [x7, #:lo12:sym]
+ ldrsb x11, [x13, :lo12:sym]
+ ldr b17, [x19, #:lo12:sym]
+// CHECK: ldrb w2, [x3, :lo12:sym]
+// CHECK: ldrsb w5, [x7, :lo12:sym]
+// CHECK: ldrsb x11, [x13, :lo12:sym]
+// CHECK: ldr b17, [x19, :lo12:sym]
+// CHECK-OBJ-ILP32 R_AARCH64_P32_LDST8_ABS_LO12_NC sym
+// CHECK-OBJ-ILP32 R_AARCH64_P32_LDST8_ABS_LO12_NC sym
+// CHECK-OBJ-ILP32 R_AARCH64_P32_LDST8_ABS_LO12_NC sym
+// CHECK-OBJ-ILP32 R_AARCH64_P32_LDST8_ABS_LO12_NC sym
+
+ ldrb w23, [x29, #:dtprel_lo12_nc:sym]
+ ldrsb w23, [x19, #:dtprel_lo12:sym]
+ ldrsb x17, [x13, :dtprel_lo12_nc:sym]
+ ldr b11, [x7, #:dtprel_lo12:sym]
+// CHECK: ldrb w23, [x29, :dtprel_lo12_nc:sym]
+// CHECK: ldrsb w23, [x19, :dtprel_lo12:sym]
+// CHECK: ldrsb x17, [x13, :dtprel_lo12_nc:sym]
+// CHECK: ldr b11, [x7, :dtprel_lo12:sym]
+// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLD_LDST8_DTPREL_LO12_NC sym
+// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLD_LDST8_DTPREL_LO12 sym
+// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLD_LDST8_DTPREL_LO12_NC sym
+// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLD_LDST8_DTPREL_LO12 sym
+
+ ldrb w1, [x2, :tprel_lo12:sym]
+ ldrsb w3, [x4, #:tprel_lo12_nc:sym]
+ ldrsb x5, [x6, :tprel_lo12:sym]
+ ldr b7, [x8, #:tprel_lo12_nc:sym]
+// CHECK: ldrb w1, [x2, :tprel_lo12:sym]
+// CHECK: ldrsb w3, [x4, :tprel_lo12_nc:sym]
+// CHECK: ldrsb x5, [x6, :tprel_lo12:sym]
+// CHECK: ldr b7, [x8, :tprel_lo12_nc:sym]
+// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLE_LDST8_TPREL_LO12 sym
+// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLE_LDST8_TPREL_LO12_NC sym
+// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLE_LDST8_TPREL_LO12 sym
+// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLE_LDST8_TPREL_LO12_NC sym
+
+ ldrh w2, [x3, #:lo12:sym]
+ ldrsh w5, [x7, :lo12:sym]
+ ldrsh x11, [x13, #:lo12:sym]
+ ldr h17, [x19, :lo12:sym]
+// CHECK: ldrh w2, [x3, :lo12:sym]
+// CHECK: ldrsh w5, [x7, :lo12:sym]
+// CHECK: ldrsh x11, [x13, :lo12:sym]
+// CHECK: ldr h17, [x19, :lo12:sym]
+// CHECK-OBJ-ILP32 R_AARCH64_P32_LDST16_ABS_LO12_NC sym
+// CHECK-OBJ-ILP32 R_AARCH64_P32_LDST16_ABS_LO12_NC sym
+// CHECK-OBJ-ILP32 R_AARCH64_P32_LDST16_ABS_LO12_NC sym
+// CHECK-OBJ-ILP32 R_AARCH64_P32_LDST16_ABS_LO12_NC sym
+
+ ldrh w23, [x29, #:dtprel_lo12_nc:sym]
+ ldrsh w23, [x19, :dtprel_lo12:sym]
+ ldrsh x17, [x13, :dtprel_lo12_nc:sym]
+ ldr h11, [x7, #:dtprel_lo12:sym]
+// CHECK: ldrh w23, [x29, :dtprel_lo12_nc:sym]
+// CHECK: ldrsh w23, [x19, :dtprel_lo12:sym]
+// CHECK: ldrsh x17, [x13, :dtprel_lo12_nc:sym]
+// CHECK: ldr h11, [x7, :dtprel_lo12:sym]
+// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLD_LDST16_DTPREL_LO12_NC sym
+// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLD_LDST16_DTPREL_LO12 sym
+// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLD_LDST16_DTPREL_LO12_NC sym
+// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLD_LDST16_DTPREL_LO12 sym
+
+ ldrh w1, [x2, :tprel_lo12:sym]
+ ldrsh w3, [x4, #:tprel_lo12_nc:sym]
+ ldrsh x5, [x6, :tprel_lo12:sym]
+ ldr h7, [x8, #:tprel_lo12_nc:sym]
+// CHECK: ldrh w1, [x2, :tprel_lo12:sym]
+// CHECK: ldrsh w3, [x4, :tprel_lo12_nc:sym]
+// CHECK: ldrsh x5, [x6, :tprel_lo12:sym]
+// CHECK: ldr h7, [x8, :tprel_lo12_nc:sym]
+// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLE_LDST16_TPREL_LO12 sym
+// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLE_LDST16_TPREL_LO12_NC sym
+// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLE_LDST16_TPREL_LO12 sym
+// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLE_LDST16_TPREL_LO12_NC sym
+
+ ldr w1, [x2, #:lo12:sym]
+ ldrsw x3, [x4, #:lo12:sym]
+ ldr s4, [x5, :lo12:sym]
+// CHECK: ldr w1, [x2, :lo12:sym]
+// CHECK: ldrsw x3, [x4, :lo12:sym]
+// CHECK: ldr s4, [x5, :lo12:sym]
+// CHECK-OBJ-ILP32 R_AARCH64_P32_LDST32_ABS_LO12_NC sym
+// CHECK-OBJ-ILP32 R_AARCH64_P32_LDST32_ABS_LO12_NC sym
+// CHECK-OBJ-ILP32 R_AARCH64_P32_LDST32_ABS_LO12_NC sym
+
+ ldr w1, [x2, :dtprel_lo12:sym]
+ ldrsw x3, [x4, #:dtprel_lo12_nc:sym]
+ ldr s4, [x5, #:dtprel_lo12_nc:sym]
+// CHECK: ldr w1, [x2, :dtprel_lo12:sym]
+// CHECK: ldrsw x3, [x4, :dtprel_lo12_nc:sym]
+// CHECK: ldr s4, [x5, :dtprel_lo12_nc:sym]
+// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLD_LDST32_DTPREL_LO12 sym
+// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLD_LDST32_DTPREL_LO12_NC sym
+// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLD_LDST32_DTPREL_LO12_NC sym
+
+
+ ldr w1, [x2, #:tprel_lo12:sym]
+ ldrsw x3, [x4, :tprel_lo12_nc:sym]
+ ldr s4, [x5, :tprel_lo12_nc:sym]
+// CHECK: ldr w1, [x2, :tprel_lo12:sym]
+// CHECK: ldrsw x3, [x4, :tprel_lo12_nc:sym]
+// CHECK: ldr s4, [x5, :tprel_lo12_nc:sym]
+// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLE_LDST32_TPREL_LO12 sym
+// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLE_LDST32_TPREL_LO12_NC sym
+// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLE_LDST32_TPREL_LO12_NC sym
+
+ ldr x28, [x27, :lo12:sym]
+ ldr d26, [x25, #:lo12:sym]
+// CHECK: ldr x28, [x27, :lo12:sym]
+// CHECK: ldr d26, [x25, :lo12:sym]
+// CHECK-OBJ-ILP32 R_AARCH64_P32_LDST64_ABS_LO12_NC sym
+// CHECK-OBJ-ILP32 R_AARCH64_P32_LDST64_ABS_LO12_NC sym
+
+ ldr x24, [x23, #:got_lo12:sym]
+ ldr d22, [x21, :got_lo12:sym]
+// CHECK: ldr x24, [x23, :got_lo12:sym]
+// CHECK: ldr d22, [x21, :got_lo12:sym]
+// CHECK-OBJ-ILP32 R_AARCH64_LD32_GOT_LO12_NC sym
+// CHECK-OBJ-ILP32 R_AARCH64_LD32_GOT_LO12_NC sym
+
+ ldr x24, [x23, :dtprel_lo12_nc:sym]
+ ldr d22, [x21, #:dtprel_lo12:sym]
+// CHECK: ldr x24, [x23, :dtprel_lo12_nc:sym]
+// CHECK: ldr d22, [x21, :dtprel_lo12:sym]
+// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLD_LDST64_DTPREL_LO12_NC sym
+// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLD_LDST64_DTPREL_LO12 sym
+
+ ldr x24, [x23, #:tprel_lo12:sym]
+ ldr d22, [x21, :tprel_lo12_nc:sym]
+// CHECK: ldr x24, [x23, :tprel_lo12:sym]
+// CHECK: ldr d22, [x21, :tprel_lo12_nc:sym]
+// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLE_LDST64_TPREL_LO12 sym
+// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLE_LDST64_TPREL_LO12_NC sym
+
+# ldr x24, [x23, :gottprel_lo12:sym]
+# ldr d22, [x21, #:gottprel_lo12:sym]
+
+ ldr x24, [x23, #:tlsdesc_lo12:sym]
+ ldr d22, [x21, :tlsdesc_lo12:sym]
+// CHECK: ldr x24, [x23, :tlsdesc_lo12:sym]
+// CHECK: ldr d22, [x21, :tlsdesc_lo12:sym]
+// Why is there a "_NC" at the end? "ELF for the ARM 64-bit architecture
+// (AArch64) beta" doesn't have that.
+// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSDESC_LD32_LO12_NC sym
+// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSDESC_LD64_LO12_NC sym
+
+ ldr q20, [x19, #:lo12:sym]
+// CHECK: ldr q20, [x19, :lo12:sym]
+// CHECK-OBJ-ILP32 R_AARCH64_P32_LDST128_ABS_LO12_NC sym
+
+// Since relocated instructions print without a '#', that syntax should
+// certainly be accepted when assembling.
+ add x3, x5, :lo12:imm
+// CHECK: add x3, x5, :lo12:imm
diff --git a/llvm/test/MC/AArch64/arm64-elf-relocs.s b/llvm/test/MC/AArch64/arm64-elf-relocs.s
index 612819cc553..0e4efed7821 100644
--- a/llvm/test/MC/AArch64/arm64-elf-relocs.s
+++ b/llvm/test/MC/AArch64/arm64-elf-relocs.s
@@ -1,83 +1,85 @@
// RUN: llvm-mc -triple=arm64-linux-gnu -o - < %s | FileCheck %s
-// RUN: llvm-mc -triple=arm64-linux-gnu -filetype=obj < %s | llvm-objdump -triple=arm64-linux-gnu - -r | FileCheck %s --check-prefix=CHECK-OBJ
+// RUN: llvm-mc -triple=arm64-linux-gnu -filetype=obj < %s | \
+// RUN: llvm-objdump -triple=arm64-linux-gnu - -r | \
+// RUN: FileCheck %s --check-prefix=CHECK-OBJ-LP64
add x0, x2, #:lo12:sym
// CHECK: add x0, x2, :lo12:sym
-// CHECK-OBJ: 0 R_AARCH64_ADD_ABS_LO12_NC sym
+// CHECK-OBJ-LP64: 0 R_AARCH64_ADD_ABS_LO12_NC sym
add x5, x7, #:dtprel_lo12:sym
// CHECK: add x5, x7, :dtprel_lo12:sym
-// CHECK-OBJ: 4 R_AARCH64_TLSLD_ADD_DTPREL_LO12 sym
+// CHECK-OBJ-LP64: 4 R_AARCH64_TLSLD_ADD_DTPREL_LO12 sym
add x9, x12, #:dtprel_lo12_nc:sym
// CHECK: add x9, x12, :dtprel_lo12_nc:sym
-// CHECK-OBJ: 8 R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC sym
+// CHECK-OBJ-LP64: 8 R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC sym
add x20, x30, #:tprel_lo12:sym
// CHECK: add x20, x30, :tprel_lo12:sym
-// CHECK-OBJ: c R_AARCH64_TLSLE_ADD_TPREL_LO12 sym
+// CHECK-OBJ-LP64: c R_AARCH64_TLSLE_ADD_TPREL_LO12 sym
add x9, x12, #:tprel_lo12_nc:sym
// CHECK: add x9, x12, :tprel_lo12_nc:sym
-// CHECK-OBJ: 10 R_AARCH64_TLSLE_ADD_TPREL_LO12_NC sym
+// CHECK-OBJ-LP64: 10 R_AARCH64_TLSLE_ADD_TPREL_LO12_NC sym
add x5, x0, #:tlsdesc_lo12:sym
// CHECK: add x5, x0, :tlsdesc_lo12:sym
-// CHECK-OBJ: 14 R_AARCH64_TLSDESC_ADD_LO12_NC sym
+// CHECK-OBJ-LP64: 14 R_AARCH64_TLSDESC_ADD_LO12_NC sym
add x0, x2, #:lo12:sym+8
// CHECK: add x0, x2, :lo12:sym
-// CHECK-OBJ: 18 R_AARCH64_ADD_ABS_LO12_NC sym+8
+// CHECK-OBJ-LP64: 18 R_AARCH64_ADD_ABS_LO12_NC sym+8
add x5, x7, #:dtprel_lo12:sym+1
// CHECK: add x5, x7, :dtprel_lo12:sym+1
-// CHECK-OBJ: 1c R_AARCH64_TLSLD_ADD_DTPREL_LO12 sym+1
+// CHECK-OBJ-LP64: 1c R_AARCH64_TLSLD_ADD_DTPREL_LO12 sym+1
add x9, x12, #:dtprel_lo12_nc:sym+2
// CHECK: add x9, x12, :dtprel_lo12_nc:sym+2
-// CHECK-OBJ:20 R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC sym+2
+// CHECK-OBJ-LP64:20 R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC sym+2
add x20, x30, #:tprel_lo12:sym+12
// CHECK: add x20, x30, :tprel_lo12:sym+12
-// CHECK-OBJ: 24 R_AARCH64_TLSLE_ADD_TPREL_LO12 sym+12
+// CHECK-OBJ-LP64: 24 R_AARCH64_TLSLE_ADD_TPREL_LO12 sym+12
add x9, x12, #:tprel_lo12_nc:sym+54
// CHECK: add x9, x12, :tprel_lo12_nc:sym+54
-// CHECK-OBJ: 28 R_AARCH64_TLSLE_ADD_TPREL_LO12_NC sym+54
+// CHECK-OBJ-LP64: 28 R_AARCH64_TLSLE_ADD_TPREL_LO12_NC sym+54
add x5, x0, #:tlsdesc_lo12:sym+70
// CHECK: add x5, x0, :tlsdesc_lo12:sym+70
-// CHECK-OBJ: 2c R_AARCH64_TLSDESC_ADD_LO12_NC sym+70
+// CHECK-OBJ-LP64: 2c R_AARCH64_TLSDESC_ADD_LO12_NC sym+70
.hword sym + 4 - .
-// CHECK-OBJ: 30 R_AARCH64_PREL16 sym+4
+// CHECK-OBJ-LP64: 30 R_AARCH64_PREL16 sym+4
.word sym - . + 8
-// CHECK-OBJ: 32 R_AARCH64_PREL32 sym+8
+// CHECK-OBJ-LP64 32 R_AARCH64_PREL32 sym+8
.xword sym-.
-// CHECK-OBJ: 36 R_AARCH64_PREL64 sym{{$}}
+// CHECK-OBJ-LP64 36 R_AARCH64_PREL64 sym{{$}}
.hword sym
-// CHECK-OBJ: 3e R_AARCH64_ABS16 sym
+// CHECK-OBJ-LP64 3e R_AARCH64_ABS16 sym
.word sym+1
-// CHECK-OBJ: 40 R_AARCH64_ABS32 sym+1
+// CHECK-OBJ-LP64 40 R_AARCH64_ABS32 sym+1
.xword sym+16
-// CHECK-OBJ: 44 R_AARCH64_ABS64 sym+16
+// CHECK-OBJ-LP64 44 R_AARCH64_ABS64 sym+16
adrp x0, sym
// CHECK: adrp x0, sym
-// CHECK-OBJ: 4c R_AARCH64_ADR_PREL_PG_HI21 sym
+// CHECK-OBJ-LP64 4c R_AARCH64_ADR_PREL_PG_HI21 sym
adrp x15, :got:sym
// CHECK: adrp x15, :got:sym
-// CHECK-OBJ: 50 R_AARCH64_ADR_GOT_PAGE sym
+// CHECK-OBJ-LP64 50 R_AARCH64_ADR_GOT_PAGE sym
adrp x29, :gottprel:sym
// CHECK: adrp x29, :gottprel:sym
-// CHECK-OBJ: 54 R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21 sym
+// CHECK-OBJ-LP64 54 R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21 sym
adrp x2, :tlsdesc:sym
// CHECK: adrp x2, :tlsdesc:sym
-// CHECK-OBJ: 58 R_AARCH64_TLSDESC_ADR_PAGE21 sym
+// CHECK-OBJ-LP64 58 R_AARCH64_TLSDESC_ADR_PAGE21 sym
// LLVM is not competent enough to do this relocation because the
// page boundary could occur anywhere after linking. A relocation
@@ -86,7 +88,7 @@
.global trickQuestion
trickQuestion:
// CHECK: adrp x3, trickQuestion
-// CHECK-OBJ: 5c R_AARCH64_ADR_PREL_PG_HI21 trickQuestion
+// CHECK-OBJ-LP64 5c R_AARCH64_ADR_PREL_PG_HI21 trickQuestion
ldrb w2, [x3, :lo12:sym]
ldrsb w5, [x7, #:lo12:sym]
@@ -96,10 +98,10 @@ trickQuestion:
// CHECK: ldrsb w5, [x7, :lo12:sym]
// CHECK: ldrsb x11, [x13, :lo12:sym]
// CHECK: ldr b17, [x19, :lo12:sym]
-// CHECK-OBJ: R_AARCH64_LDST8_ABS_LO12_NC sym
-// CHECK-OBJ: R_AARCH64_LDST8_ABS_LO12_NC sym
-// CHECK-OBJ: R_AARCH64_LDST8_ABS_LO12_NC sym
-// CHECK-OBJ: R_AARCH64_LDST8_ABS_LO12_NC sym
+// CHECK-OBJ-LP64 R_AARCH64_LDST8_ABS_LO12_NC sym
+// CHECK-OBJ-LP64 R_AARCH64_LDST8_ABS_LO12_NC sym
+// CHECK-OBJ-LP64 R_AARCH64_LDST8_ABS_LO12_NC sym
+// CHECK-OBJ-LP64 R_AARCH64_LDST8_ABS_LO12_NC sym
ldrb w23, [x29, #:dtprel_lo12_nc:sym]
ldrsb w23, [x19, #:dtprel_lo12:sym]
@@ -109,10 +111,10 @@ trickQuestion:
// CHECK: ldrsb w23, [x19, :dtprel_lo12:sym]
// CHECK: ldrsb x17, [x13, :dtprel_lo12_nc:sym]
// CHECK: ldr b11, [x7, :dtprel_lo12:sym]
-// CHECK-OBJ: R_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC sym
-// CHECK-OBJ: R_AARCH64_TLSLD_LDST8_DTPREL_LO12 sym
-// CHECK-OBJ: R_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC sym
-// CHECK-OBJ: R_AARCH64_TLSLD_LDST8_DTPREL_LO12 sym
+// CHECK-OBJ-LP64 R_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC sym
+// CHECK-OBJ-LP64 R_AARCH64_TLSLD_LDST8_DTPREL_LO12 sym
+// CHECK-OBJ-LP64 R_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC sym
+// CHECK-OBJ-LP64 R_AARCH64_TLSLD_LDST8_DTPREL_LO12 sym
ldrb w1, [x2, :tprel_lo12:sym]
ldrsb w3, [x4, #:tprel_lo12_nc:sym]
@@ -122,10 +124,10 @@ trickQuestion:
// CHECK: ldrsb w3, [x4, :tprel_lo12_nc:sym]
// CHECK: ldrsb x5, [x6, :tprel_lo12:sym]
// CHECK: ldr b7, [x8, :tprel_lo12_nc:sym]
-// CHECK-OBJ: R_AARCH64_TLSLE_LDST8_TPREL_LO12 sym
-// CHECK-OBJ: R_AARCH64_TLSLE_LDST8_TPREL_LO12_NC sym
-// CHECK-OBJ: R_AARCH64_TLSLE_LDST8_TPREL_LO12 sym
-// CHECK-OBJ: R_AARCH64_TLSLE_LDST8_TPREL_LO12_NC sym
+// CHECK-OBJ-LP64 R_AARCH64_TLSLE_LDST8_TPREL_LO12 sym
+// CHECK-OBJ-LP64 R_AARCH64_TLSLE_LDST8_TPREL_LO12_NC sym
+// CHECK-OBJ-LP64 R_AARCH64_TLSLE_LDST8_TPREL_LO12 sym
+// CHECK-OBJ-LP64 R_AARCH64_TLSLE_LDST8_TPREL_LO12_NC sym
ldrh w2, [x3, #:lo12:sym]
ldrsh w5, [x7, :lo12:sym]
@@ -135,10 +137,10 @@ trickQuestion:
// CHECK: ldrsh w5, [x7, :lo12:sym]
// CHECK: ldrsh x11, [x13, :lo12:sym]
// CHECK: ldr h17, [x19, :lo12:sym]
-// CHECK-OBJ: R_AARCH64_LDST16_ABS_LO12_NC sym
-// CHECK-OBJ: R_AARCH64_LDST16_ABS_LO12_NC sym
-// CHECK-OBJ: R_AARCH64_LDST16_ABS_LO12_NC sym
-// CHECK-OBJ: R_AARCH64_LDST16_ABS_LO12_NC sym
+// CHECK-OBJ-LP64 R_AARCH64_LDST16_ABS_LO12_NC sym
+// CHECK-OBJ-LP64 R_AARCH64_LDST16_ABS_LO12_NC sym
+// CHECK-OBJ-LP64 R_AARCH64_LDST16_ABS_LO12_NC sym
+// CHECK-OBJ-LP64 R_AARCH64_LDST16_ABS_LO12_NC sym
ldrh w23, [x29, #:dtprel_lo12_nc:sym]
ldrsh w23, [x19, :dtprel_lo12:sym]
@@ -148,10 +150,10 @@ trickQuestion:
// CHECK: ldrsh w23, [x19, :dtprel_lo12:sym]
// CHECK: ldrsh x17, [x13, :dtprel_lo12_nc:sym]
// CHECK: ldr h11, [x7, :dtprel_lo12:sym]
-// CHECK-OBJ: R_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC sym
-// CHECK-OBJ: R_AARCH64_TLSLD_LDST16_DTPREL_LO12 sym
-// CHECK-OBJ: R_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC sym
-// CHECK-OBJ: R_AARCH64_TLSLD_LDST16_DTPREL_LO12 sym
+// CHECK-OBJ-LP64 R_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC sym
+// CHECK-OBJ-LP64 R_AARCH64_TLSLD_LDST16_DTPREL_LO12 sym
+// CHECK-OBJ-LP64 R_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC sym
+// CHECK-OBJ-LP64 R_AARCH64_TLSLD_LDST16_DTPREL_LO12 sym
ldrh w1, [x2, :tprel_lo12:sym]
ldrsh w3, [x4, #:tprel_lo12_nc:sym]
@@ -161,10 +163,10 @@ trickQuestion:
// CHECK: ldrsh w3, [x4, :tprel_lo12_nc:sym]
// CHECK: ldrsh x5, [x6, :tprel_lo12:sym]
// CHECK: ldr h7, [x8, :tprel_lo12_nc:sym]
-// CHECK-OBJ: R_AARCH64_TLSLE_LDST16_TPREL_LO12 sym
-// CHECK-OBJ: R_AARCH64_TLSLE_LDST16_TPREL_LO12_NC sym
-// CHECK-OBJ: R_AARCH64_TLSLE_LDST16_TPREL_LO12 sym
-// CHECK-OBJ: R_AARCH64_TLSLE_LDST16_TPREL_LO12_NC sym
+// CHECK-OBJ-LP64 R_AARCH64_TLSLE_LDST16_TPREL_LO12 sym
+// CHECK-OBJ-LP64 R_AARCH64_TLSLE_LDST16_TPREL_LO12_NC sym
+// CHECK-OBJ-LP64 R_AARCH64_TLSLE_LDST16_TPREL_LO12 sym
+// CHECK-OBJ-LP64 R_AARCH64_TLSLE_LDST16_TPREL_LO12_NC sym
ldr w1, [x2, #:lo12:sym]
ldrsw x3, [x4, #:lo12:sym]
@@ -172,9 +174,9 @@ trickQuestion:
// CHECK: ldr w1, [x2, :lo12:sym]
// CHECK: ldrsw x3, [x4, :lo12:sym]
// CHECK: ldr s4, [x5, :lo12:sym]
-// CHECK-OBJ: R_AARCH64_LDST32_ABS_LO12_NC sym
-// CHECK-OBJ: R_AARCH64_LDST32_ABS_LO12_NC sym
-// CHECK-OBJ: R_AARCH64_LDST32_ABS_LO12_NC sym
+// CHECK-OBJ-LP64 R_AARCH64_LDST32_ABS_LO12_NC sym
+// CHECK-OBJ-LP64 R_AARCH64_LDST32_ABS_LO12_NC sym
+// CHECK-OBJ-LP64 R_AARCH64_LDST32_ABS_LO12_NC sym
ldr w1, [x2, :dtprel_lo12:sym]
ldrsw x3, [x4, #:dtprel_lo12_nc:sym]
@@ -182,9 +184,9 @@ trickQuestion:
// CHECK: ldr w1, [x2, :dtprel_lo12:sym]
// CHECK: ldrsw x3, [x4, :dtprel_lo12_nc:sym]
// CHECK: ldr s4, [x5, :dtprel_lo12_nc:sym]
-// CHECK-OBJ: R_AARCH64_TLSLD_LDST32_DTPREL_LO12 sym
-// CHECK-OBJ: R_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC sym
-// CHECK-OBJ: R_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC sym
+// CHECK-OBJ-LP64 R_AARCH64_TLSLD_LDST32_DTPREL_LO12 sym
+// CHECK-OBJ-LP64 R_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC sym
+// CHECK-OBJ-LP64 R_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC sym
ldr w1, [x2, #:tprel_lo12:sym]
@@ -193,55 +195,55 @@ trickQuestion:
// CHECK: ldr w1, [x2, :tprel_lo12:sym]
// CHECK: ldrsw x3, [x4, :tprel_lo12_nc:sym]
// CHECK: ldr s4, [x5, :tprel_lo12_nc:sym]
-// CHECK-OBJ: R_AARCH64_TLSLE_LDST32_TPREL_LO12 sym
-// CHECK-OBJ: R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC sym
-// CHECK-OBJ: R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC sym
+// CHECK-OBJ-LP64 R_AARCH64_TLSLE_LDST32_TPREL_LO12 sym
+// CHECK-OBJ-LP64 R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC sym
+// CHECK-OBJ-LP64 R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC sym
ldr x28, [x27, :lo12:sym]
ldr d26, [x25, #:lo12:sym]
// CHECK: ldr x28, [x27, :lo12:sym]
// CHECK: ldr d26, [x25, :lo12:sym]
-// CHECK-OBJ: R_AARCH64_LDST64_ABS_LO12_NC sym
-// CHECK-OBJ: R_AARCH64_LDST64_ABS_LO12_NC sym
+// CHECK-OBJ-LP64 R_AARCH64_LDST64_ABS_LO12_NC sym
+// CHECK-OBJ-LP64 R_AARCH64_LDST64_ABS_LO12_NC sym
ldr x24, [x23, #:got_lo12:sym]
ldr d22, [x21, :got_lo12:sym]
// CHECK: ldr x24, [x23, :got_lo12:sym]
// CHECK: ldr d22, [x21, :got_lo12:sym]
-// CHECK-OBJ: R_AARCH64_LD64_GOT_LO12_NC sym
-// CHECK-OBJ: R_AARCH64_LD64_GOT_LO12_NC sym
+// CHECK-OBJ-LP64 R_AARCH64_LD64_GOT_LO12_NC sym
+// CHECK-OBJ-LP64 R_AARCH64_LD64_GOT_LO12_NC sym
ldr x24, [x23, :dtprel_lo12_nc:sym]
ldr d22, [x21, #:dtprel_lo12:sym]
// CHECK: ldr x24, [x23, :dtprel_lo12_nc:sym]
// CHECK: ldr d22, [x21, :dtprel_lo12:sym]
-// CHECK-OBJ: R_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC sym
-// CHECK-OBJ: R_AARCH64_TLSLD_LDST64_DTPREL_LO12 sym
+// CHECK-OBJ-LP64 R_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC sym
+// CHECK-OBJ-LP64 R_AARCH64_TLSLD_LDST64_DTPREL_LO12 sym
ldr x24, [x23, #:tprel_lo12:sym]
ldr d22, [x21, :tprel_lo12_nc:sym]
// CHECK: ldr x24, [x23, :tprel_lo12:sym]
// CHECK: ldr d22, [x21, :tprel_lo12_nc:sym]
-// CHECK-OBJ: R_AARCH64_TLSLE_LDST64_TPREL_LO12 sym
-// CHECK-OBJ: R_AARCH64_TLSLE_LDST64_TPREL_LO12_NC sym
+// CHECK-OBJ-LP64 R_AARCH64_TLSLE_LDST64_TPREL_LO12 sym
+// CHECK-OBJ-LP64 R_AARCH64_TLSLE_LDST64_TPREL_LO12_NC sym
ldr x24, [x23, :gottprel_lo12:sym]
ldr d22, [x21, #:gottprel_lo12:sym]
// CHECK: ldr x24, [x23, :gottprel_lo12:sym]
// CHECK: ldr d22, [x21, :gottprel_lo12:sym]
-// CHECK-OBJ: R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC sym
-// CHECK-OBJ: R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC sym
+// CHECK-OBJ-LP64 R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC sym
+// CHECK-OBJ-LP64 R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC sym
ldr x24, [x23, #:tlsdesc_lo12:sym]
ldr d22, [x21, :tlsdesc_lo12:sym]
// CHECK: ldr x24, [x23, :tlsdesc_lo12:sym]
// CHECK: ldr d22, [x21, :tlsdesc_lo12:sym]
-// CHECK-OBJ: R_AARCH64_TLSDESC_LD64_LO12_NC sym
-// CHECK-OBJ: R_AARCH64_TLSDESC_LD64_LO12_NC sym
+// CHECK-OBJ-LP64 R_AARCH64_TLSDESC_LD64_LO12_NC sym
+// CHECK-OBJ-LP64 R_AARCH64_TLSDESC_LD64_LO12_NC sym
ldr q20, [x19, #:lo12:sym]
// CHECK: ldr q20, [x19, :lo12:sym]
-// CHECK-OBJ: R_AARCH64_LDST128_ABS_LO12_NC sym
+// CHECK-OBJ-LP64 R_AARCH64_LDST128_ABS_LO12_NC sym
// Since relocated instructions print without a '#', that syntax should
// certainly be accepted when assembling.
diff --git a/llvm/test/MC/AArch64/arm64-ilp32.s b/llvm/test/MC/AArch64/arm64-ilp32.s
new file mode 100644
index 00000000000..3e9f44abd70
--- /dev/null
+++ b/llvm/test/MC/AArch64/arm64-ilp32.s
@@ -0,0 +1,37 @@
+// RUN: llvm-mc -target-abi=ilp32 -triple aarch64-non-linux-gnu -filetype=obj \
+// RUN: %s | llvm-objdump -r - | FileCheck --check-prefix=CHECK-ILP32 %s
+// RUN: llvm-mc -triple aarch64-non-linux-gnu -filetype=obj \
+// RUN: %s | llvm-objdump -r - | FileCheck --check-prefix=CHECK-LP64 %s
+ .text
+ .file "../projects/clang/test/Driver/arm64-ilp32.c"
+ .globl foo
+ .align 2
+ .type foo,@function
+foo: // @foo
+// BB#0: // %entry
+ sub sp, sp, #16 // =16
+// CHECK-ILP32: 0000000000000004 R_AARCH64_P32_ADR_PREL_PG_HI21 sizes
+// CHECK-ILP32: 0000000000000008 R_AARCH64_P32_ADD_ABS_LO12_NC sizes
+// CHECK-LP64: 0000000000000004 R_AARCH64_ADR_PREL_PG_HI21 sizes
+// CHECK-LP64: 0000000000000008 R_AARCH64_ADD_ABS_LO12_NC sizes
+ adrp x8, sizes
+ add x8, x8, :lo12:sizes
+ str w0, [sp, #12]
+ str w1, [sp, #8]
+ ldr w0, [x8]
+ add sp, sp, #16 // =16
+ ret
+.Lfunc_end0:
+ .size foo, .Lfunc_end0-foo
+
+ .type sizes,@object // @sizes
+ .data
+ .globl sizes
+ .align 2
+sizes:
+ .word 1 // 0x1
+ .word 2 // 0x2
+ .word 4 // 0x4
+ .word 4 // 0x4
+ .word 4 // 0x4
+ .size sizes, 20
diff --git a/llvm/test/MC/AArch64/ilp32-diagnostics.s b/llvm/test/MC/AArch64/ilp32-diagnostics.s
new file mode 100644
index 00000000000..47c24e242a1
--- /dev/null
+++ b/llvm/test/MC/AArch64/ilp32-diagnostics.s
@@ -0,0 +1,67 @@
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -target-abi=ilp32 \
+// RUN: < %s 2> %t2 -filetype=obj
+// RUN: FileCheck --check-prefix=CHECK-ERROR %s < %t2
+
+ .xword sym-.
+// CHECK-ERROR: error: ILP32 8 byte PC relative data relocation not supported (LP64 eqv: PREL64)
+// CHECK-ERROR: ^
+
+ movz x7, #:abs_g3:some_label
+// CHECK-ERROR: error: ILP32 absolute MOV relocation not supported (LP64 eqv: MOVW_UABS_G3)
+// CHECK-ERROR: movz x7, #:abs_g3:some_label
+// CHECK-ERROR: ^
+
+ movz x3, #:abs_g2:some_label
+// CHECK-ERROR: error: ILP32 absolute MOV relocation not supported (LP64 eqv: MOVW_UABS_G2)
+// CHECK-ERROR: movz x3, #:abs_g2:some_label
+// CHECK-ERROR: ^
+
+ movz x19, #:abs_g2_s:some_label
+// CHECK-ERROR: error: ILP32 absolute MOV relocation not supported (LP64 eqv: MOVW_SABS_G2)
+// CHECK-ERROR: movz x19, #:abs_g2_s:some_label
+// CHECK-ERROR: ^
+
+ movk x5, #:abs_g2_nc:some_label
+// CHECK-ERROR: error: ILP32 absolute MOV relocation not supported (LP64 eqv: MOVW_UABS_G2_NC)
+// CHECK-ERROR: movk x5, #:abs_g2_nc:some_label
+// CHECK-ERROR: ^
+
+ movz x19, #:abs_g1_s:some_label
+// CHECK-ERROR: error: ILP32 absolute MOV relocation not supported (LP64 eqv: MOVW_SABS_G1)
+// CHECK-ERROR: movz x19, #:abs_g1_s:some_label
+// CHECK-ERROR: ^
+
+ movk x5, #:abs_g1_nc:some_label
+// CHECK-ERROR: error: ILP32 absolute MOV relocation not supported (LP64 eqv: MOVW_UABS_G1_NC)
+// CHECK-ERROR: movk x5, #:abs_g1_nc:some_label
+// CHECK-ERROR: ^
+
+ movz x3, #:dtprel_g2:var
+// CHECK-ERROR: error: ILP32 absolute MOV relocation not supported (LP64 eqv: TLSLD_MOVW_DTPREL_G2)
+// CHECK-ERROR: movz x3, #:dtprel_g2:var
+// CHECK-ERROR: ^
+
+ movk x9, #:dtprel_g1_nc:var
+// CHECK-ERROR: error: ILP32 absolute MOV relocation not supported (LP64 eqv: TLSLD_MOVW_DTPREL_G1_NC)
+// CHECK-ERROR: movk x9, #:dtprel_g1_nc:var
+// CHECK-ERROR: ^
+
+ movz x3, #:tprel_g2:var
+// CHECK-ERROR: error: ILP32 absolute MOV relocation not supported (LP64 eqv: TLSLE_MOVW_TPREL_G2)
+// CHECK-ERROR: movz x3, #:tprel_g2:var
+// CHECK-ERROR: ^
+
+ movk x9, #:tprel_g1_nc:var
+// CHECK-ERROR: error: ILP32 absolute MOV relocation not supported (LP64 eqv: TLSLE_MOVW_TPREL_G1_NC)
+// CHECK-ERROR: movk x9, #:tprel_g1_nc:var
+// CHECK-ERROR: ^
+
+ movz x15, #:gottprel_g1:var
+// CHECK-ERROR: error: ILP32 absolute MOV relocation not supported (LP64 eqv: TLSIE_MOVW_GOTTPREL_G1)
+// CHECK-ERROR: movz x15, #:gottprel_g1:var
+// CHECK-ERROR: ^
+
+ movk x13, #:gottprel_g0_nc:var
+// CHECK-ERROR: error: ILP32 absolute MOV relocation not supported (LP64 eqv: TLSIE_MOVW_GOTTPREL_G0_NC)
+// CHECK-ERROR: movk x13, #:gottprel_g0_nc:var
+// CHECK-ERROR: ^
diff --git a/llvm/test/tools/llvm-readobj/Inputs/relocs.obj.elf-aarch64-ilp32 b/llvm/test/tools/llvm-readobj/Inputs/relocs.obj.elf-aarch64-ilp32
new file mode 100644
index 00000000000..e69de29bb2d
--- /dev/null
+++ b/llvm/test/tools/llvm-readobj/Inputs/relocs.obj.elf-aarch64-ilp32
diff --git a/llvm/test/tools/llvm-readobj/Inputs/relocs.py b/llvm/test/tools/llvm-readobj/Inputs/relocs.py
index 48a1ffb0994..3d0cae567e5 100644
--- a/llvm/test/tools/llvm-readobj/Inputs/relocs.py
+++ b/llvm/test/tools/llvm-readobj/Inputs/relocs.py
@@ -715,6 +715,94 @@ class Relocs_Elf_AArch64(Enum):
R_AARCH64_TLSDESC = 0x407
R_AARCH64_IRELATIVE = 0x408
+class Relocs_Elf_AArch64_ILP32(Enum):
+ R_AARCH64_P32_NONE = 0
+ R_AARCH64_P32_ABS32 = 1
+ R_AARCH64_P32_ABS16 = 2
+ R_AARCH64_P32_PREL32 = 3
+ R_AARCH64_P32_PREL16 = 4
+ R_AARCH64_P32_MOVW_UABS_G0 = 5
+ R_AARCH64_P32_MOVW_UABS_G0_NC = 6
+ R_AARCH64_P32_MOVW_UABS_G1 = 7
+ R_AARCH64_P32_MOVW_SABS_G0 = 8
+ R_AARCH64_P32_LD_PREL_LO19 = 9
+ R_AARCH64_P32_ADR_PREL_LO21 = 10
+ R_AARCH64_P32_ADR_PREL_PG_HI21 = 11
+ R_AARCH64_P32_ADD_ABS_LO12_NC = 12
+ R_AARCH64_P32_LDST8_ABS_LO12_NC = 13
+ R_AARCH64_P32_LDST16_ABS_LO12_NC = 14
+ R_AARCH64_P32_LDST32_ABS_LO12_NC = 15
+ R_AARCH64_P32_LDST64_ABS_LO12_NC = 16
+ R_AARCH64_P32_LDST128_ABS_LO12_NC = 17
+ R_AARCH64_P32_TSTBR14 = 18
+ R_AARCH64_P32_CONDBR19 = 19
+ R_AARCH64_P32_JUMP26 = 20
+ R_AARCH64_P32_CALL26 = 21
+ R_AARCH64_P32_MOVW_PREL_G0 = 22
+ R_AARCH64_P32_MOVW_PREL_G0_NC = 23
+ R_AARCH64_P32_MOVW_PREL_G1 = 24
+ R_AARCH64_P32_GOT_LD_PREL19 = 25
+ R_AARCH64_P32_ADR_GOT_PAGE = 26
+ R_AARCH64_P32_LD32_GOT_LO12_NC = 27
+ R_AARCH64_P32_LD32_GOTPAGE_LO14 = 28
+ R_AARCH64_P32_TLSGD_ADR_PREL21 = 80
+ R_AARCH64_P32_TLS_GD_ADR_PAGE21 = 81
+ R_AARCH64_P32_TLSGD_ADD_LO12_NC = 82
+ R_AARCH64_P32_TLSLD_ADR_PREL21 = 83
+ R_AARCH64_P32_TLDLD_ADR_PAGE21 = 84
+ R_AARCH64_P32_TLSLD_ADR_LO12_NC = 85
+ R_AARCH64_P32_TLSLD_LD_PREL19 = 86
+ R_AARCH64_P32_TLDLD_MOVW_DTPREL_G1 = 87
+ R_AARCH64_P32_TLSLD_MOVW_DTPREL_G0 = 88
+ R_AARCH64_P32_TLSLD_MOVW_DTPREL_G0_NC = 89
+ R_AARCH64_P32_TLSLD_MOVW_ADD_DTPREL_HI12 = 90
+ R_AARCH64_P32_TLSLD_ADD_DTPREL_LO12 = 91
+ R_AARCH64_P32_TLSLD_ADD_DTPREL_LO12_NC = 92
+ R_AARCH64_P32_TLSLD_LDST8_DTPREL_LO12 = 93
+ R_AARCH64_P32_TLSLD_LDST8_DTPREL_LO12_NC = 94
+ R_AARCH64_P32_TLSLD_LDST16_DTPREL_LO12 = 95
+ R_AARCH64_P32_TLSLD_LDST16_DTPREL_LO12_NC = 96
+ R_AARCH64_P32_TLSLD_LDST32_DTPREL_LO12 = 97
+ R_AARCH64_P32_TLSLD_LDST32_DTPREL_LO12_NC = 98
+ R_AARCH64_P32_TLSLD_LDST64_DTPREL_LO12 = 99
+ R_AARCH64_P32_TLSLD_LDST64_DTPREL_LO12_NC = 100
+ R_AARCH64_P32_TLSLD_LDST128_DTPREL_LO12 = 101
+ R_AARCH64_P32_TLSLD_LDST128_DTPREL_LO12_NC = 102
+ R_AARCH64_P32_TLSIE_MOVW_GOTTPREL_PAGE21 = 103
+ R_AARCH64_P32_TLSIE_LD32_GOTTPREL_LO12_NC = 104
+ R_AARCH64_P32_TLSIE_LD_GOTTPREL_PREL19 = 105
+ R_AARCH64_P32_TLSLE_MOVEW_TPREL_G1 = 106
+ R_AARCH64_P32_TLSLE_MOVW_TPREL_G0 = 107
+ R_AARCH64_P32_TLSLE_MOVW_TPREL_G0_NC = 108
+ R_AARCH64_P32_TLS_MOVW_TPREL_HI12 = 109
+ R_AARCH64_P32_TLSLE_ADD_TPREL_LO12 = 110
+ R_AARCH64_P32_TLSLE_ADD_TPREL_LO12_NC = 111
+ R_AARCH64_P32_TLSLE_LDST8_TPREL_LO12 = 112
+ R_AARCH64_P32_TLSLE_LDST8_TPREL_LO12_NC = 113
+ R_AARCH64_P32_TLSLE_LDST16_TPREL_LO12 = 114
+ R_AARCH64_P32_TLSLE_LDST16_TPREL_LO12_NC = 115
+ R_AARCH64_P32_TLSLE_LDST32_TPREL_LO12 = 116
+ R_AARCH64_P32_TLSLE_LDST32_TPREL_LO12_NC = 117
+ R_AARCH64_P32_TLSLE_LDST64_TPREL_LO12 = 118
+ R_AARCH64_P32_TLSLE_LDST64_TPREL_LO12_NC = 119
+ R_AARCH64_P32_TLSLE_LDST128_TPREL_LO12 = 120
+ R_AARCH64_P32_TLSLE_LDST128_TPREL_LO12_NC = 121
+ R_AARCH64_P32_TLSDESC_LD_PRELL19 = 122
+ R_AARCH64_P32_TLSDESC_ADR_PREL21 = 123
+ R_AARCH64_P32_TLSDESC_ADR_PAGE21 = 124
+ R_AARCH64_P32_TLSDESSC_LD32_LO12 = 125
+ R_AARCH64_P32_TLSDESC_ADD_LO12 = 126
+ R_AARCH64_P32_TLSDESC_CALL = 127
+ R_AARCH64_P32_COPY = 180
+ R_AARCH64_P32_GLOB_DAT = 181
+ R_AARCH64_P32_JUMP_SLOT = 182
+ R_AARCH64_P32_RELATIVE = 183
+ R_AARCH64_P32_TLS_DTPREL = 184
+ R_AARCH64_P32_TLS_DTPMOD = 185
+ R_AARCH64_P32_TLS_TPREL = 186
+ R_AARCH64_P32_TLSDESC = 187
+ R_AARCH64_P32_IRELATIVE = 188
+
class Relocs_Elf_ARM(Enum):
R_ARM_NONE = 0x00
R_ARM_PC24 = 0x01
@@ -1107,6 +1195,9 @@ craftElf("relocs.obj.elf-i386", "i386-pc-linux-gnu", Relocs_Elf_i3
craftElf("relocs.obj.elf-ppc64", "powerpc64-unknown-linux-gnu", Relocs_Elf_PPC64.entries(),
("@t = thread_local global i32 0, align 4", "define i32* @f{0}() nounwind {{ ret i32* @t }}", 2))
craftElf("relocs.obj.elf-aarch64", "aarch64", Relocs_Elf_AArch64.entries(), "movz x0, #:abs_g0:sym")
+craftElf("relocs.obj.elf-aarch64-ilp32", "aarch64",
+ Relocs_Elf_AArch64_ILP32.entries(), "movz x0, #:abs_g0:sym")
+Relocs_Elf_AArch64_ILP32
craftElf("relocs.obj.elf-arm", "arm-unknown-unknown", Relocs_Elf_ARM.entries(), "b sym")
craftElf("relocs.obj.elf-mips", "mips-unknown-linux", Relocs_Elf_Mips.entries(), "lui $2, %hi(sym)")
craftElf("relocs.obj.elf-mips64el", "mips64el-unknown-linux", Relocs_Elf_Mips.entries(), "lui $2, %hi(sym)")
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