diff options
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/collapse-endcf.mir | 150 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.swap.ll | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/si-lower-control-flow.mir | 69 |
3 files changed, 56 insertions, 165 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/collapse-endcf.mir b/llvm/test/CodeGen/AMDGPU/collapse-endcf.mir index aad00387224..708814e3df4 100644 --- a/llvm/test/CodeGen/AMDGPU/collapse-endcf.mir +++ b/llvm/test/CodeGen/AMDGPU/collapse-endcf.mir @@ -49,10 +49,8 @@ body: | ; GCN: successors: %bb.4(0x80000000) ; GCN: DBG_VALUE ; GCN: bb.4: - ; GCN: successors: %bb.5(0x80000000) ; GCN: DBG_VALUE - ; GCN: $exec = S_OR_B64_term $exec, [[COPY2]], implicit-def $scc - ; GCN: bb.5: + ; GCN: $exec = S_OR_B64 $exec, [[COPY2]], implicit-def $scc ; GCN: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 3, implicit $exec ; GCN: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec ; GCN: $m0 = S_MOV_B32 -1 @@ -97,14 +95,12 @@ body: | BUFFER_STORE_DWORD_ADDR64 %14, %8, %5, 0, 4, 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1) bb.3: + $exec = S_OR_B64 $exec, %12, implicit-def $scc DBG_VALUE - $exec = S_OR_B64_term $exec, %12, implicit-def $scc bb.4: DBG_VALUE - $exec = S_OR_B64_term $exec, %3, implicit-def $scc - - bb.5: + $exec = S_OR_B64 $exec, %3, implicit-def $scc %15:vgpr_32 = V_MOV_B32_e32 3, implicit $exec %16:vgpr_32 = V_MOV_B32_e32 0, implicit $exec $m0 = S_MOV_B32 -1 @@ -125,7 +121,7 @@ machineFunctionInfo: body: | ; GCN-LABEL: name: simple_nested_if_empty_block_between ; GCN: bb.0: - ; GCN: successors: %bb.1(0x40000000), %bb.4(0x40000000) + ; GCN: successors: %bb.1(0x40000000), %bb.5(0x40000000) ; GCN: liveins: $vgpr0, $sgpr0_sgpr1 ; GCN: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr0_sgpr1 ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0 @@ -133,7 +129,7 @@ body: | ; GCN: [[COPY2:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec ; GCN: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY2]], [[V_CMP_LT_U32_e64_]], implicit-def dead $scc ; GCN: $exec = S_MOV_B64_term [[S_AND_B64_]] - ; GCN: SI_MASK_BRANCH %bb.4, implicit $exec + ; GCN: SI_MASK_BRANCH %bb.5, implicit $exec ; GCN: S_BRANCH %bb.1 ; GCN: bb.1: ; GCN: successors: %bb.2(0x40000000), %bb.3(0x40000000) @@ -162,9 +158,7 @@ body: | ; GCN: bb.4: ; GCN: successors: %bb.5(0x80000000) ; GCN: bb.5: - ; GCN: successors: %bb.6(0x80000000) - ; GCN: $exec = S_OR_B64_term $exec, [[COPY2]], implicit-def $scc - ; GCN: bb.6: + ; GCN: $exec = S_OR_B64 $exec, [[COPY2]], implicit-def $scc ; GCN: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 3, implicit $exec ; GCN: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec ; GCN: $m0 = S_MOV_B32 -1 @@ -209,14 +203,12 @@ body: | BUFFER_STORE_DWORD_ADDR64 %14, %8, %5, 0, 4, 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1) bb.3: - $exec = S_OR_B64_term $exec, %12, implicit-def $scc - - bb.4: + $exec = S_OR_B64 $exec, %12, implicit-def $scc bb.5: - $exec = S_OR_B64_term $exec, %3, implicit-def $scc - bb.6: + bb.4: + $exec = S_OR_B64 $exec, %3, implicit-def $scc %15:vgpr_32 = V_MOV_B32_e32 3, implicit $exec %16:vgpr_32 = V_MOV_B32_e32 0, implicit $exec $m0 = S_MOV_B32 -1 @@ -237,7 +229,7 @@ machineFunctionInfo: body: | ; GCN-LABEL: name: simple_nested_if_empty_block_dbg_between ; GCN: bb.0: - ; GCN: successors: %bb.1(0x40000000), %bb.4(0x40000000) + ; GCN: successors: %bb.1(0x40000000), %bb.5(0x40000000) ; GCN: liveins: $vgpr0, $sgpr0_sgpr1 ; GCN: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr0_sgpr1 ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0 @@ -275,9 +267,7 @@ body: | ; GCN: successors: %bb.5(0x80000000) ; GCN: DBG_VALUE ; GCN: bb.5: - ; GCN: successors: %bb.6(0x80000000) - ; GCN: $exec = S_OR_B64_term $exec, [[COPY2]], implicit-def $scc - ; GCN: bb.6: + ; GCN: $exec = S_OR_B64 $exec, [[COPY2]], implicit-def $scc ; GCN: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 3, implicit $exec ; GCN: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec ; GCN: $m0 = S_MOV_B32 -1 @@ -293,7 +283,7 @@ body: | %3:sreg_64 = COPY $exec, implicit-def $exec %4:sreg_64 = S_AND_B64 %3, %2, implicit-def dead $scc $exec = S_MOV_B64_term %4 - SI_MASK_BRANCH %bb.5, implicit $exec + SI_MASK_BRANCH %bb.4, implicit $exec S_BRANCH %bb.1 bb.1: @@ -322,15 +312,13 @@ body: | BUFFER_STORE_DWORD_ADDR64 %14, %8, %5, 0, 4, 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1) bb.3: - $exec = S_OR_B64_term $exec, %12, implicit-def $scc - - bb.4: - DBG_VALUE + $exec = S_OR_B64 $exec, %12, implicit-def $scc bb.5: - $exec = S_OR_B64_term $exec, %3, implicit-def $scc + DBG_VALUE - bb.6: + bb.4: + $exec = S_OR_B64 $exec, %3, implicit-def $scc %15:vgpr_32 = V_MOV_B32_e32 3, implicit $exec %16:vgpr_32 = V_MOV_B32_e32 0, implicit $exec $m0 = S_MOV_B32 -1 @@ -372,7 +360,8 @@ body: | ; GCN: %5.sub2:sgpr_128 = S_MOV_B32 0 ; GCN: BUFFER_STORE_DWORD_ADDR64 %6.sub1, %6, %5, 0, 0, 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1) ; GCN: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 2, [[COPY1]], implicit $exec - ; GCN: [[S_AND_B64_1:%[0-9]+]]:sreg_64 = S_AND_B64 $exec, [[V_CMP_NE_U32_e64_]], implicit-def dead $scc + ; GCN: [[COPY4:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec + ; GCN: [[S_AND_B64_1:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY4]], [[V_CMP_NE_U32_e64_]], implicit-def dead $scc ; GCN: $exec = S_MOV_B64_term [[S_AND_B64_1]] ; GCN: SI_MASK_BRANCH %bb.3, implicit $exec ; GCN: S_BRANCH %bb.2 @@ -387,10 +376,9 @@ body: | ; GCN: [[DEF:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF ; GCN: dead %16:sgpr_32 = S_BREV_B32 [[DEF]] ; GCN: KILL [[DEF]] + ; GCN: $exec = S_OR_B64 $exec, [[COPY4]], implicit-def $scc ; GCN: bb.4: - ; GCN: successors: %bb.5(0x80000000) - ; GCN: $exec = S_OR_B64_term $exec, [[COPY2]], implicit-def $scc - ; GCN: bb.5: + ; GCN: $exec = S_OR_B64 $exec, [[COPY2]], implicit-def $scc ; GCN: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 3, implicit $exec ; GCN: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec ; GCN: $m0 = S_MOV_B32 -1 @@ -438,12 +426,10 @@ body: | %15:sgpr_32 = IMPLICIT_DEF %16:sgpr_32 = S_BREV_B32 %15 KILL %15 - $exec = S_OR_B64_term $exec, %12, implicit-def $scc + $exec = S_OR_B64 $exec, %12, implicit-def $scc bb.4: - $exec = S_OR_B64_term $exec, %3, implicit-def $scc - - bb.5: + $exec = S_OR_B64 $exec, %3, implicit-def $scc %17:vgpr_32 = V_MOV_B32_e32 3, implicit $exec %18:vgpr_32 = V_MOV_B32_e32 0, implicit $exec $m0 = S_MOV_B32 -1 @@ -489,7 +475,7 @@ body: | ; GCN: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 2, [[COPY1]], implicit $exec ; GCN: [[S_AND_B64_1:%[0-9]+]]:sreg_64 = S_AND_B64 $exec, [[V_CMP_NE_U32_e64_]], implicit-def dead $scc ; GCN: $exec = S_MOV_B64_term [[S_AND_B64_1]] - ; GCN: SI_MASK_BRANCH %bb.4, implicit $exec + ; GCN: SI_MASK_BRANCH %bb.3, implicit $exec ; GCN: S_BRANCH %bb.2 ; GCN: bb.2: ; GCN: successors: %bb.3(0x80000000) @@ -499,16 +485,12 @@ body: | ; GCN: BUFFER_STORE_DWORD_ADDR64 [[V_MOV_B32_e32_]], %8, %5, 0, 4, 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1) ; GCN: bb.3: ; GCN: successors: %bb.4(0x80000000) - ; GCN: bb.4: - ; GCN: successors: %bb.5(0x80000000) ; GCN: [[DEF:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF ; GCN: [[S_BREV_B32_:%[0-9]+]]:sgpr_32 = S_BREV_B32 [[DEF]] ; GCN: KILL [[DEF]] ; GCN: dead %17:sgpr_32 = COPY [[S_BREV_B32_]] - ; GCN: bb.5: - ; GCN: successors: %bb.6(0x80000000) - ; GCN: $exec = S_OR_B64_term $exec, [[COPY2]], implicit-def $scc - ; GCN: bb.6: + ; GCN: bb.4: + ; GCN: $exec = S_OR_B64 $exec, [[COPY2]], implicit-def $scc ; GCN: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 3, implicit $exec ; GCN: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec ; GCN: $m0 = S_MOV_B32 -1 @@ -543,7 +525,7 @@ body: | %12:sreg_64 = COPY $exec, implicit-def $exec %13:sreg_64 = S_AND_B64 %12, %11, implicit-def dead $scc $exec = S_MOV_B64_term %13 - SI_MASK_BRANCH %bb.4, implicit $exec + SI_MASK_BRANCH %bb.3, implicit $exec S_BRANCH %bb.2 bb.2: @@ -553,18 +535,14 @@ body: | BUFFER_STORE_DWORD_ADDR64 %14, %8, %5, 0, 4, 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1) bb.3: - $exec = S_OR_B64_term $exec, %12, implicit-def $scc - - bb.4: + $exec = S_OR_B64 $exec, %12, implicit-def $scc %15:sgpr_32 = IMPLICIT_DEF %16:sgpr_32 = S_BREV_B32 %15 KILL %15 %19:sgpr_32 = COPY %16 - bb.5: - $exec = S_OR_B64_term $exec, %3, implicit-def $scc - - bb.6: + bb.4: + $exec = S_OR_B64 $exec, %3, implicit-def $scc %17:vgpr_32 = V_MOV_B32_e32 3, implicit $exec %18:vgpr_32 = V_MOV_B32_e32 0, implicit $exec $m0 = S_MOV_B32 -1 @@ -620,14 +598,10 @@ body: | ; GCN: BUFFER_STORE_DWORD_ADDR64 [[V_MOV_B32_e32_]], %8, %5, 0, 4, 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1) ; GCN: bb.3: ; GCN: successors: %bb.4(0x80000000) - ; GCN: $exec = S_OR_B64_term $exec, [[COPY4]], implicit-def $scc - ; GCN: bb.4: - ; GCN: successors: %bb.5(0x80000000) + ; GCN: $exec = S_OR_B64 $exec, [[COPY4]], implicit-def $scc ; GCN: dead %15:sreg_64 = S_BREV_B64 $exec - ; GCN: bb.5: - ; GCN: successors: %bb.6(0x80000000) - ; GCN: $exec = S_OR_B64_term $exec, [[COPY2]], implicit-def $scc - ; GCN: bb.6: + ; GCN: bb.4: + ; GCN: $exec = S_OR_B64 $exec, [[COPY2]], implicit-def $scc ; GCN: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 3, implicit $exec ; GCN: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec ; GCN: $m0 = S_MOV_B32 -1 @@ -672,15 +646,11 @@ body: | BUFFER_STORE_DWORD_ADDR64 %14, %8, %5, 0, 4, 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1) bb.3: - $exec = S_OR_B64_term $exec, %12, implicit-def $scc - - bb.4: + $exec = S_OR_B64 $exec, %12, implicit-def $scc %15:sreg_64 = S_BREV_B64 $exec - bb.5: - $exec = S_OR_B64_term $exec, %3, implicit-def $scc - - bb.6: + bb.4: + $exec = S_OR_B64 $exec, %3, implicit-def $scc %17:vgpr_32 = V_MOV_B32_e32 3, implicit $exec %18:vgpr_32 = V_MOV_B32_e32 0, implicit $exec $m0 = S_MOV_B32 -1 @@ -701,7 +671,7 @@ machineFunctionInfo: body: | ; GCN-LABEL: name: copy_no_explicit_exec_dependency ; GCN: bb.0: - ; GCN: successors: %bb.1(0x40000000), %bb.5(0x40000000) + ; GCN: successors: %bb.1(0x40000000), %bb.4(0x40000000) ; GCN: liveins: $vgpr0, $sgpr0_sgpr1 ; GCN: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr0_sgpr1 ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0 @@ -709,7 +679,7 @@ body: | ; GCN: [[COPY2:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec ; GCN: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY2]], [[V_CMP_LT_U32_e64_]], implicit-def dead $scc ; GCN: $exec = S_MOV_B64_term [[S_AND_B64_]] - ; GCN: SI_MASK_BRANCH %bb.5, implicit $exec + ; GCN: SI_MASK_BRANCH %bb.4, implicit $exec ; GCN: S_BRANCH %bb.1 ; GCN: bb.1: ; GCN: successors: %bb.2(0x40000000), %bb.3(0x40000000) @@ -736,21 +706,17 @@ body: | ; GCN: BUFFER_STORE_DWORD_ADDR64 [[V_MOV_B32_e32_]], %8, %5, 0, 4, 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1) ; GCN: bb.3: ; GCN: successors: %bb.4(0x80000000) - ; GCN: $exec = S_OR_B64_term $exec, [[COPY4]], implicit-def $scc - ; GCN: bb.4: - ; GCN: successors: %bb.5(0x80000000) + ; GCN: $exec = S_OR_B64 $exec, [[COPY4]], implicit-def $scc ; GCN: dead %15:vgpr_32 = COPY %5.sub2 - ; GCN: bb.5: - ; GCN: successors: %bb.6(0x80000000) - ; GCN: $exec = S_OR_B64_term $exec, [[COPY2]], implicit-def $scc - ; GCN: bb.6: + ; GCN: bb.4: + ; GCN: $exec = S_OR_B64 $exec, [[COPY2]], implicit-def $scc ; GCN: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 3, implicit $exec ; GCN: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec ; GCN: $m0 = S_MOV_B32 -1 ; GCN: DS_WRITE_B32 [[V_MOV_B32_e32_2]], [[V_MOV_B32_e32_1]], 0, 0, implicit $m0, implicit $exec :: (store 4, addrspace 3) ; GCN: S_ENDPGM 0 bb.0: - successors: %bb.1, %bb.5 + successors: %bb.1, %bb.4 liveins: $vgpr0, $sgpr0_sgpr1 %1:sgpr_64 = COPY $sgpr0_sgpr1 @@ -759,7 +725,7 @@ body: | %3:sreg_64 = COPY $exec, implicit-def $exec %4:sreg_64 = S_AND_B64 %3, %2, implicit-def dead $scc $exec = S_MOV_B64_term %4 - SI_MASK_BRANCH %bb.5, implicit $exec + SI_MASK_BRANCH %bb.4, implicit $exec S_BRANCH %bb.1 bb.1: @@ -788,15 +754,11 @@ body: | BUFFER_STORE_DWORD_ADDR64 %14, %8, %5, 0, 4, 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1) bb.3: - $exec = S_OR_B64_term $exec, %12, implicit-def $scc - - bb.4: + $exec = S_OR_B64 $exec, %12, implicit-def $scc %15:vgpr_32 = COPY %5.sub2 - bb.5: - $exec = S_OR_B64_term $exec, %3, implicit-def $scc - - bb.6: + bb.4: + $exec = S_OR_B64 $exec, %3, implicit-def $scc %17:vgpr_32 = V_MOV_B32_e32 3, implicit $exec %18:vgpr_32 = V_MOV_B32_e32 0, implicit $exec $m0 = S_MOV_B32 -1 @@ -851,19 +813,17 @@ body: | ; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec ; GCN: BUFFER_STORE_DWORD_ADDR64 [[V_MOV_B32_e32_]], %8, %5, 0, 4, 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1) ; GCN: bb.3: - ; GCN: successors: %bb.6(0x80000000) - ; GCN: $exec = S_OR_B64_term $exec, [[COPY4]], implicit-def $scc - ; GCN: S_BRANCH %bb.6 - ; GCN: bb.4: ; GCN: successors: %bb.5(0x80000000) - ; GCN: $exec = S_OR_B64_term $exec, [[COPY2]], implicit-def $scc - ; GCN: bb.5: + ; GCN: $exec = S_OR_B64 $exec, [[COPY4]], implicit-def $scc + ; GCN: S_BRANCH %bb.5 + ; GCN: bb.4: + ; GCN: $exec = S_OR_B64 $exec, [[COPY2]], implicit-def $scc ; GCN: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 3, implicit $exec ; GCN: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec ; GCN: $m0 = S_MOV_B32 -1 ; GCN: DS_WRITE_B32 [[V_MOV_B32_e32_2]], [[V_MOV_B32_e32_1]], 0, 0, implicit $m0, implicit $exec :: (store 4, addrspace 3) ; GCN: S_ENDPGM 0 - ; GCN: bb.6: + ; GCN: bb.5: ; GCN: successors: %bb.4(0x80000000) ; GCN: S_BRANCH %bb.4 bb.0: @@ -905,20 +865,18 @@ body: | BUFFER_STORE_DWORD_ADDR64 %14, %8, %5, 0, 4, 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1) bb.3: - $exec = S_OR_B64_term $exec, %12, implicit-def $scc - S_BRANCH %bb.6 + $exec = S_OR_B64 $exec, %12, implicit-def $scc + S_BRANCH %bb.5 bb.4: - $exec = S_OR_B64_term $exec, %3, implicit-def $scc - - bb.5: + $exec = S_OR_B64 $exec, %3, implicit-def $scc %15:vgpr_32 = V_MOV_B32_e32 3, implicit $exec %16:vgpr_32 = V_MOV_B32_e32 0, implicit $exec $m0 = S_MOV_B32 -1 DS_WRITE_B32 %16, %15, 0, 0, implicit $m0, implicit $exec :: (store 4, addrspace 3) S_ENDPGM 0 - bb.6: + bb.5: S_BRANCH %bb.4 ... diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.swap.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.swap.ll index 3d457c4ce7f..acb1133c6a0 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.swap.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.swap.ll @@ -21,7 +21,7 @@ define amdgpu_cs float @ds_ordered_swap(i32 addrspace(2)* inreg %gds, i32 %value ; GCN: s_cbranch_execz [[BB:BB._.]] ; GCN: s_mov_b32 m0, s0 ; VIGFX9-NEXT: s_nop 0 -; GCN-NEXT: ds_ordered_count v1, v0 offset:4868 gds +; GCN-NEXT: ds_ordered_count v{{[0-9]+}}, v0 offset:4868 gds ; GCN-NEXT: [[BB]]: ; // Wait for expcnt(0) before modifying EXEC ; GCN-NEXT: s_waitcnt expcnt(0) diff --git a/llvm/test/CodeGen/AMDGPU/si-lower-control-flow.mir b/llvm/test/CodeGen/AMDGPU/si-lower-control-flow.mir index 944e10b4f19..fdb0c465c20 100644 --- a/llvm/test/CodeGen/AMDGPU/si-lower-control-flow.mir +++ b/llvm/test/CodeGen/AMDGPU/si-lower-control-flow.mir @@ -10,7 +10,7 @@ body: | bb.0: ; GCN-LABEL: name: si-lower-control-flow ; GCN: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5 - ; GCN: [[S_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM [[COPY]], 16, 0, 0 + ; GCN: [[S_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM [[COPY]], 16, 0 ; GCN: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0 = S_AND_B32 [[S_LOAD_DWORD_IMM]], 255, implicit-def $scc ; GCN: [[S_AND_B32_1:%[0-9]+]]:sreg_32_xm0 = S_AND_B32 65535, [[S_AND_B32_]], implicit-def $scc ; GCN: S_ENDPGM 0 @@ -51,70 +51,3 @@ body: | S_ENDPGM 0 ... - ---- -name: si_end_cf_lower_iterator_assert -tracksRegLiveness: true -body: | - ; GCN-LABEL: name: si_end_cf_lower_iterator_assert - ; GCN: bb.0: - ; GCN: successors: %bb.1(0x40000000), %bb.2(0x40000000) - ; GCN: liveins: $sgpr30_sgpr31 - ; GCN: [[COPY:%[0-9]+]]:sreg_64 = COPY killed $sgpr30_sgpr31 - ; GCN: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0 - ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF - ; GCN: [[V_CMP_NEQ_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NEQ_F32_e64 0, 0, 0, killed [[DEF]], 0, implicit $exec - ; GCN: [[COPY1:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec - ; GCN: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY1]], killed [[V_CMP_NEQ_F32_e64_]], implicit-def dead $scc - ; GCN: $exec = S_MOV_B64_term killed [[S_AND_B64_]] - ; GCN: SI_MASK_BRANCH %bb.2, implicit $exec - ; GCN: S_BRANCH %bb.1 - ; GCN: bb.1: - ; GCN: successors: %bb.2(0x80000000) - ; GCN: bb.2: - ; GCN: successors: %bb.6(0x80000000) - ; GCN: $exec = S_OR_B64_term $exec, killed [[COPY1]], implicit-def $scc - ; GCN: bb.6: - ; GCN: successors: %bb.3(0x80000000) - ; GCN: [[S_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM killed [[S_MOV_B64_]], 0, 0, 0 :: (load 4, addrspace 4) - ; GCN: bb.3: - ; GCN: successors: %bb.5(0x40000000), %bb.4(0x40000000) - ; GCN: S_CMP_EQ_U32 killed [[S_LOAD_DWORD_IMM]], 1, implicit-def $scc - ; GCN: S_CBRANCH_SCC1 %bb.5, implicit killed $scc - ; GCN: S_BRANCH %bb.4 - ; GCN: bb.4: - ; GCN: successors: %bb.5(0x80000000) - ; GCN: SI_MASKED_UNREACHABLE - ; GCN: bb.5: - ; GCN: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY killed [[COPY]] - ; GCN: S_SETPC_B64_return killed [[COPY2]] - bb.0: - successors: %bb.1, %bb.2 - liveins: $sgpr30_sgpr31 - - %11:sreg_64 = COPY killed $sgpr30_sgpr31 - %3:sreg_64 = S_MOV_B64 0 - %7:vgpr_32 = IMPLICIT_DEF - %9:sreg_64 = V_CMP_NEQ_F32_e64 0, 0, 0, killed %7, 0, implicit $exec - %2:sreg_64 = SI_IF killed %9, %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec - S_BRANCH %bb.1 - - bb.1: - - bb.2: - %4:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM killed %3, 0, 0, 0 :: (load 4, addrspace 4) - SI_END_CF killed %2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec - - bb.3: - S_CMP_EQ_U32 killed %4, 1, implicit-def $scc - S_CBRANCH_SCC1 %bb.5, implicit killed $scc - S_BRANCH %bb.4 - - bb.4: - SI_MASKED_UNREACHABLE - - bb.5: - %12:ccr_sgpr_64 = COPY killed %11 - S_SETPC_B64_return killed %12 - -... |
