diff options
Diffstat (limited to 'llvm/test')
21 files changed, 0 insertions, 478 deletions
diff --git a/llvm/test/CodeGen/Hexagon/convertdptoint.ll b/llvm/test/CodeGen/Hexagon/convertdptoint.ll deleted file mode 100644 index bbb205e8207..00000000000 --- a/llvm/test/CodeGen/Hexagon/convertdptoint.ll +++ /dev/null @@ -1,26 +0,0 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s -; Check that we generate conversion from double precision floating point -; to 32-bit int value in IEEE complaint mode in V5. - -; CHECK: r{{[0-9]+}} = convert_df2w(r{{[0-9]+}}:{{[0-9]+}}):chop - -define i32 @main() nounwind { -entry: - %retval = alloca i32, align 4 - %i = alloca i32, align 4 - %a = alloca double, align 8 - %b = alloca double, align 8 - %c = alloca double, align 8 - store i32 0, i32* %retval - store double 1.540000e+01, double* %a, align 8 - store double 9.100000e+00, double* %b, align 8 - %0 = load double* %a, align 8 - %1 = load double* %b, align 8 - %add = fadd double %0, %1 - store double %add, double* %c, align 8 - %2 = load double* %c, align 8 - %conv = fptosi double %2 to i32 - store i32 %conv, i32* %i, align 4 - %3 = load i32* %i, align 4 - ret i32 %3 -} diff --git a/llvm/test/CodeGen/Hexagon/convertdptoll.ll b/llvm/test/CodeGen/Hexagon/convertdptoll.ll deleted file mode 100644 index bded6f1853e..00000000000 --- a/llvm/test/CodeGen/Hexagon/convertdptoll.ll +++ /dev/null @@ -1,27 +0,0 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s -; Check that we generate conversion from double precision floating point -; to 64-bit integer value in IEEE complaint mode in V5. - -; CHECK: r{{[0-9]+}} = convert_df2d(r{{[0-9]+}}:{{[0-9]+}}):chop - -define i32 @main() nounwind { -entry: - %retval = alloca i32, align 4 - %i = alloca i64, align 8 - %a = alloca double, align 8 - %b = alloca double, align 8 - %c = alloca double, align 8 - store i32 0, i32* %retval - store double 1.540000e+01, double* %a, align 8 - store double 9.100000e+00, double* %b, align 8 - %0 = load double* %a, align 8 - %1 = load double* %b, align 8 - %add = fadd double %0, %1 - store double %add, double* %c, align 8 - %2 = load double* %c, align 8 - %conv = fptosi double %2 to i64 - store i64 %conv, i64* %i, align 8 - %3 = load i64* %i, align 8 - %conv1 = trunc i64 %3 to i32 - ret i32 %conv1 -} diff --git a/llvm/test/CodeGen/Hexagon/convertsptoint.ll b/llvm/test/CodeGen/Hexagon/convertsptoint.ll deleted file mode 100644 index b8a9d6c8083..00000000000 --- a/llvm/test/CodeGen/Hexagon/convertsptoint.ll +++ /dev/null @@ -1,26 +0,0 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s -; Check that we generate conversion from single precision floating point -; to 32-bit int value in IEEE complaint mode in V5. - -; CHECK: r{{[0-9]+}} = convert_sf2w(r{{[0-9]+}}):chop - -define i32 @main() nounwind { -entry: - %retval = alloca i32, align 4 - %i = alloca i32, align 4 - %a = alloca float, align 4 - %b = alloca float, align 4 - %c = alloca float, align 4 - store i32 0, i32* %retval - store float 0x402ECCCCC0000000, float* %a, align 4 - store float 0x4022333340000000, float* %b, align 4 - %0 = load float* %a, align 4 - %1 = load float* %b, align 4 - %add = fadd float %0, %1 - store float %add, float* %c, align 4 - %2 = load float* %c, align 4 - %conv = fptosi float %2 to i32 - store i32 %conv, i32* %i, align 4 - %3 = load i32* %i, align 4 - ret i32 %3 -} diff --git a/llvm/test/CodeGen/Hexagon/convertsptoll.ll b/llvm/test/CodeGen/Hexagon/convertsptoll.ll deleted file mode 100644 index a35484b0feb..00000000000 --- a/llvm/test/CodeGen/Hexagon/convertsptoll.ll +++ /dev/null @@ -1,27 +0,0 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s -; Check that we generate conversion from single precision floating point -; to 64-bit int value in IEEE complaint mode in V5. - -; CHECK: r{{[0-9]+}} = convert_sf2d(r{{[0-9]+}}) - -define i32 @main() nounwind { -entry: - %retval = alloca i32, align 4 - %i = alloca i64, align 8 - %a = alloca float, align 4 - %b = alloca float, align 4 - %c = alloca float, align 4 - store i32 0, i32* %retval - store float 0x402ECCCCC0000000, float* %a, align 4 - store float 0x4022333340000000, float* %b, align 4 - %0 = load float* %a, align 4 - %1 = load float* %b, align 4 - %add = fadd float %0, %1 - store float %add, float* %c, align 4 - %2 = load float* %c, align 4 - %conv = fptosi float %2 to i64 - store i64 %conv, i64* %i, align 8 - %3 = load i64* %i, align 8 - %conv1 = trunc i64 %3 to i32 - ret i32 %conv1 -} diff --git a/llvm/test/CodeGen/Hexagon/dadd.ll b/llvm/test/CodeGen/Hexagon/dadd.ll deleted file mode 100644 index b7ecaa45215..00000000000 --- a/llvm/test/CodeGen/Hexagon/dadd.ll +++ /dev/null @@ -1,19 +0,0 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s -; Check that we generate double precision floating point add in V5. - -; CHECK: r{{[0-9]+}} = dfadd(r{{[0-9]+}}, r{{[0-9]+}}) - - -define i32 @main() nounwind { -entry: - %a = alloca double, align 8 - %b = alloca double, align 8 - %c = alloca double, align 8 - store double 1.540000e+01, double* %a, align 8 - store double 9.100000e+00, double* %b, align 8 - %0 = load double* %a, align 8 - %1 = load double* %b, align 8 - %add = fadd double %0, %1 - store double %add, double* %c, align 8 - ret i32 0 -} diff --git a/llvm/test/CodeGen/Hexagon/dmul.ll b/llvm/test/CodeGen/Hexagon/dmul.ll deleted file mode 100644 index d7437739ee9..00000000000 --- a/llvm/test/CodeGen/Hexagon/dmul.ll +++ /dev/null @@ -1,18 +0,0 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s -; Check that we generate double precision floating point multiply in V5. - -; CHECK: r{{[0-9]+}}:{{[0-9]+}} = dfmpy(r{{[0-9]+}}:{{[0-9]+}}, r{{[0-9]+}}:{{[0-9]+}}) - -define i32 @main() nounwind { -entry: - %a = alloca double, align 8 - %b = alloca double, align 8 - %c = alloca double, align 8 - store double 1.540000e+01, double* %a, align 8 - store double 9.100000e+00, double* %b, align 8 - %0 = load double* %b, align 8 - %1 = load double* %a, align 8 - %mul = fmul double %0, %1 - store double %mul, double* %c, align 8 - ret i32 0 -} diff --git a/llvm/test/CodeGen/Hexagon/doubleconvert-ieee-rnd-near.ll b/llvm/test/CodeGen/Hexagon/doubleconvert-ieee-rnd-near.ll deleted file mode 100644 index ff2f0e8a7b0..00000000000 --- a/llvm/test/CodeGen/Hexagon/doubleconvert-ieee-rnd-near.ll +++ /dev/null @@ -1,26 +0,0 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv5 -enable-hexagon-ieee-rnd-near < %s | FileCheck %s -; Check that we generate conversion from double precision floating point -; to 32-bit int value in IEEE rounding to the nearest mode in V5. - -; CHECK: r{{[0-9]+}} = convert_df2w(r{{[0-9]+}}:{{[0-9]+}}) - -define i32 @main() nounwind { -entry: - %retval = alloca i32, align 4 - %i = alloca i32, align 4 - %a = alloca double, align 8 - %b = alloca double, align 8 - %c = alloca double, align 8 - store i32 0, i32* %retval - store double 1.540000e+01, double* %a, align 8 - store double 9.100000e+00, double* %b, align 8 - %0 = load double* %a, align 8 - %1 = load double* %b, align 8 - %add = fadd double %0, %1 - store double %add, double* %c, align 8 - %2 = load double* %c, align 8 - %conv = fptosi double %2 to i32 - store i32 %conv, i32* %i, align 4 - %3 = load i32* %i, align 4 - ret i32 %3 -} diff --git a/llvm/test/CodeGen/Hexagon/dsub.ll b/llvm/test/CodeGen/Hexagon/dsub.ll deleted file mode 100644 index 3f50c77871d..00000000000 --- a/llvm/test/CodeGen/Hexagon/dsub.ll +++ /dev/null @@ -1,18 +0,0 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s -; Check that we generate double precision floating point subtract in V5. - -; CHECK: r{{[0-9]+}} = dfsub(r{{[0-9]+}}, r{{[0-9]+}}) - -define i32 @main() nounwind { -entry: - %a = alloca double, align 8 - %b = alloca double, align 8 - %c = alloca double, align 8 - store double 1.540000e+01, double* %a, align 8 - store double 9.100000e+00, double* %b, align 8 - %0 = load double* %b, align 8 - %1 = load double* %a, align 8 - %sub = fsub double %0, %1 - store double %sub, double* %c, align 8 - ret i32 0 -} diff --git a/llvm/test/CodeGen/Hexagon/dualstore.ll b/llvm/test/CodeGen/Hexagon/dualstore.ll deleted file mode 100644 index add5e477e1e..00000000000 --- a/llvm/test/CodeGen/Hexagon/dualstore.ll +++ /dev/null @@ -1,19 +0,0 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s -; Check that we generate dual stores in one packet in V4 - -; CHECK: { -; CHECK-NEXT: memw(r{{[0-9]+}} + #{{[0-9]+}} = r{{[0-9]+}} -; CHECK-NEXT: memw(r{{[0-9]+}} + #{{[0-9]+}} = r{{[0-9]+}} -; CHECK-NEXT: } - - -@Reg = global i32 0, align 4 -define i32 @main() nounwind { -entry: - %number= alloca i32, align 4 - store i32 500000, i32* %number, align 4 - %number1= alloca i32, align 4 - store i32 100000, i32* %number1, align 4 - ret i32 0 -} - diff --git a/llvm/test/CodeGen/Hexagon/fadd.ll b/llvm/test/CodeGen/Hexagon/fadd.ll deleted file mode 100644 index b95e1475ff7..00000000000 --- a/llvm/test/CodeGen/Hexagon/fadd.ll +++ /dev/null @@ -1,18 +0,0 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s -; Check that we generate sp floating point add in V5. - -; CHECK: r{{[0-9]+}} = sfadd(r{{[0-9]+}}, r{{[0-9]+}}) - -define i32 @main() nounwind { -entry: - %a = alloca float, align 4 - %b = alloca float, align 4 - %c = alloca float, align 4 - store float 0x402ECCCCC0000000, float* %a, align 4 - store float 0x4022333340000000, float* %b, align 4 - %0 = load float* %a, align 4 - %1 = load float* %b, align 4 - %add = fadd float %0, %1 - store float %add, float* %c, align 4 - ret i32 0 -} diff --git a/llvm/test/CodeGen/Hexagon/fcmp.ll b/llvm/test/CodeGen/Hexagon/fcmp.ll deleted file mode 100644 index e7b649e2b8c..00000000000 --- a/llvm/test/CodeGen/Hexagon/fcmp.ll +++ /dev/null @@ -1,37 +0,0 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s -; Check that we generate floating point compare in V5 - -; CHECK: p{{[0-2]+}} = sfcmp.{{.}} - -define i32 @foo(float %y) nounwind { -entry: - %retval = alloca i32, align 4 - %y.addr = alloca float, align 4 - store float %y, float* %y.addr, align 4 - %0 = load float* %y.addr, align 4 - %cmp = fcmp ogt float %0, 0x406AD7EFA0000000 - br i1 %cmp, label %if.then, label %if.else - -if.then: ; preds = %entry - store i32 1, i32* %retval - br label %return - -if.else: ; preds = %entry - store i32 2, i32* %retval - br label %return - -return: ; preds = %if.else, %if.then - %1 = load i32* %retval - ret i32 %1 -} - -define i32 @main() nounwind { -entry: - %retval = alloca i32, align 4 - %a = alloca float, align 4 - store i32 0, i32* %retval - store float 0x40012E0A00000000, float* %a, align 4 - %0 = load float* %a, align 4 - %call = call i32 @foo(float %0) - ret i32 %call -} diff --git a/llvm/test/CodeGen/Hexagon/floatconvert-ieee-rnd-near.ll b/llvm/test/CodeGen/Hexagon/floatconvert-ieee-rnd-near.ll deleted file mode 100644 index da56280fe09..00000000000 --- a/llvm/test/CodeGen/Hexagon/floatconvert-ieee-rnd-near.ll +++ /dev/null @@ -1,26 +0,0 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s -; Check that we generate conversion from double precision floating point -; to 32-bit int value in IEEE rounding to the nearest mode in V5. - -; CHECK: r{{[0-9]+}} = convert_sf2w(r{{[0-9]+}}) - -define i32 @main() nounwind { -entry: - %retval = alloca i32, align 4 - %i = alloca i32, align 4 - %a = alloca float, align 4 - %b = alloca float, align 4 - %c = alloca float, align 4 - store i32 0, i32* %retval - store float 0x402ECCCCC0000000, float* %a, align 4 - store float 0x4022333340000000, float* %b, align 4 - %0 = load float* %a, align 4 - %1 = load float* %b, align 4 - %add = fadd float %0, %1 - store float %add, float* %c, align 4 - %2 = load float* %c, align 4 - %conv = fptosi float %2 to i32 - store i32 %conv, i32* %i, align 4 - %3 = load i32* %i, align 4 - ret i32 %3 -} diff --git a/llvm/test/CodeGen/Hexagon/fmul.ll b/llvm/test/CodeGen/Hexagon/fmul.ll deleted file mode 100644 index 4766845b114..00000000000 --- a/llvm/test/CodeGen/Hexagon/fmul.ll +++ /dev/null @@ -1,19 +0,0 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s -; Check that we generate single precision floating point multiply in V5. - -; CHECK: r{{[0-9]+}} = sfmpy(r{{[0-9]+}}, r{{[0-9]+}}) - - -define i32 @main() nounwind { -entry: - %a = alloca float, align 4 - %b = alloca float, align 4 - %c = alloca float, align 4 - store float 0x402ECCCCC0000000, float* %a, align 4 - store float 0x4022333340000000, float* %b, align 4 - %0 = load float* %b, align 4 - %1 = load float* %a, align 4 - %mul = fmul float %0, %1 - store float %mul, float* %c, align 4 - ret i32 0 -} diff --git a/llvm/test/CodeGen/Hexagon/fsub.ll b/llvm/test/CodeGen/Hexagon/fsub.ll deleted file mode 100644 index 07c866f4c2e..00000000000 --- a/llvm/test/CodeGen/Hexagon/fsub.ll +++ /dev/null @@ -1,18 +0,0 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s -; Check that we generate sp floating point subtract in V5. - -; CHECK: r{{[0-9]+}} = sfsub(r{{[0-9]+}}, r{{[0-9]+}}) - -define i32 @main() nounwind { -entry: - %a = alloca float, align 4 - %b = alloca float, align 4 - %c = alloca float, align 4 - store float 0x402ECCCCC0000000, float* %a, align 4 - store float 0x4022333340000000, float* %b, align 4 - %0 = load float* %b, align 4 - %1 = load float* %a, align 4 - %sub = fsub float %0, %1 - store float %sub, float* %c, align 4 - ret i32 0 -} diff --git a/llvm/test/CodeGen/Hexagon/fusedandshift.ll b/llvm/test/CodeGen/Hexagon/fusedandshift.ll deleted file mode 100644 index 022b3c67345..00000000000 --- a/llvm/test/CodeGen/Hexagon/fusedandshift.ll +++ /dev/null @@ -1,16 +0,0 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s -; Check that we generate fused logical and with shift instruction. - -; CHECK: r{{[0-9]+}} = and(#15, lsr(r{{[0-9]+}}, #{{[0-9]+}}) - -define i32 @main(i16* %a, i16* %b) nounwind { - entry: - %0 = load i16* %a, align 2 - %conv1 = sext i16 %0 to i32 - %shr1 = ashr i32 %conv1, 3 - %and1 = and i32 %shr1, 15 - %conv2 = trunc i32 %and1 to i16 - store i16 %conv2, i16* %b, align 2 - ret i32 0 -} - diff --git a/llvm/test/CodeGen/Hexagon/macint.ll b/llvm/test/CodeGen/Hexagon/macint.ll deleted file mode 100644 index fe89fe2cecd..00000000000 --- a/llvm/test/CodeGen/Hexagon/macint.ll +++ /dev/null @@ -1,14 +0,0 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s -; Check that we generate integer multiply accumulate. - -; CHECK: r{{[0-9]+}} += mpyi(r{{[0-9]+}}, r{{[0-9]+}}) - -define i32 @main(i32* %a, i32* %b) nounwind { - entry: - %0 = load i32* %a, align 4 - %div = udiv i32 %0, 10000 - %rem = urem i32 %div, 10 - store i32 %rem, i32* %b, align 4 - ret i32 0 -} - diff --git a/llvm/test/CodeGen/Hexagon/newvaluejump.ll b/llvm/test/CodeGen/Hexagon/newvaluejump.ll deleted file mode 100644 index 9c7ca55cb8f..00000000000 --- a/llvm/test/CodeGen/Hexagon/newvaluejump.ll +++ /dev/null @@ -1,33 +0,0 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s -; Check that we generate new value jump. - -@i = global i32 0, align 4 -@j = global i32 10, align 4 - -define i32 @foo(i32 %a) nounwind { -entry: -; CHECK: if (cmp.eq(r{{[0-9]+}}.new, #0)) jump{{.}} - %addr1 = alloca i32, align 4 - %addr2 = alloca i32, align 4 - %0 = load i32* @i, align 4 - store i32 %0, i32* %addr1, align 4 - call void @bar(i32 1, i32 2) - %1 = load i32* @j, align 4 - %tobool = icmp ne i32 %1, 0 - br i1 %tobool, label %if.then, label %if.else - -if.then: - call void @baz(i32 1, i32 2) - br label %if.end - -if.else: - call void @guy(i32 10, i32 20) - br label %if.end - -if.end: - ret i32 0 -} - -declare void @guy(i32, i32) -declare void @bar(i32, i32) -declare void @baz(i32, i32) diff --git a/llvm/test/CodeGen/Hexagon/newvaluejump2.ll b/llvm/test/CodeGen/Hexagon/newvaluejump2.ll deleted file mode 100644 index cb2f33e4c02..00000000000 --- a/llvm/test/CodeGen/Hexagon/newvaluejump2.ll +++ /dev/null @@ -1,30 +0,0 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s -; Check that we generate new value jump, both registers, with one -; of the registers as new. - -@Reg = common global i8 0, align 1 -define i32 @main() nounwind { -entry: -; CHECK: if (cmp.eq(r{{[0-9]+}}.new, r{{[0-9]+}})) jump{{.}} - %Reg2 = alloca i8, align 1 - %0 = load i8* %Reg2, align 1 - %conv0 = zext i8 %0 to i32 - %1 = load i8* @Reg, align 1 - %conv1 = zext i8 %1 to i32 - %tobool = icmp sle i32 %conv0, %conv1 - br i1 %tobool, label %if.then, label %if.else - -if.then: - call void @bar(i32 1, i32 2) - br label %if.end - -if.else: - call void @baz(i32 10, i32 20) - br label %if.end - -if.end: - ret i32 0 -} - -declare void @bar(i32, i32) -declare void @baz(i32, i32) diff --git a/llvm/test/CodeGen/Hexagon/newvaluestore.ll b/llvm/test/CodeGen/Hexagon/newvaluestore.ll deleted file mode 100644 index ab69b22df57..00000000000 --- a/llvm/test/CodeGen/Hexagon/newvaluestore.ll +++ /dev/null @@ -1,22 +0,0 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s -; Check that we generate new value store packet in V4 - -@i = global i32 0, align 4 -@j = global i32 10, align 4 -@k = global i32 100, align 4 - -define i32 @main() nounwind { -entry: -; CHECK: memw(r{{[0-9]+}} + #{{[0-9]+}}) = r{{[0-9]+}}.new - %number1 = alloca i32, align 4 - %number2 = alloca i32, align 4 - %number3 = alloca i32, align 4 - %0 = load i32 * @i, align 4 - store i32 %0, i32* %number1, align 4 - %1 = load i32 * @j, align 4 - store i32 %1, i32* %number2, align 4 - %2 = load i32 * @k, align 4 - store i32 %2, i32* %number3, align 4 - ret i32 %0 -} - diff --git a/llvm/test/CodeGen/Hexagon/opt-fabs.ll b/llvm/test/CodeGen/Hexagon/opt-fabs.ll deleted file mode 100644 index 1cf0dd0cd99..00000000000 --- a/llvm/test/CodeGen/Hexagon/opt-fabs.ll +++ /dev/null @@ -1,15 +0,0 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s -; Optimize fabsf to clrbit in V5. - -; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}}, #31) - -define float @my_fabsf(float %x) nounwind { -entry: - %x.addr = alloca float, align 4 - store float %x, float* %x.addr, align 4 - %0 = load float* %x.addr, align 4 - %call = call float @fabsf(float %0) - ret float %call -} - -declare float @fabsf(float) diff --git a/llvm/test/CodeGen/Hexagon/opt-fneg.ll b/llvm/test/CodeGen/Hexagon/opt-fneg.ll deleted file mode 100644 index cf7e2d571df..00000000000 --- a/llvm/test/CodeGen/Hexagon/opt-fneg.ll +++ /dev/null @@ -1,24 +0,0 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s -; Optimize fneg to togglebit in V5. - -define float @bar(float %x) nounwind { -entry: -; CHECK: r{{[0-9]+}} = togglebit(r{{[0-9]+}}, #31) - %x.addr = alloca float, align 4 - store float %x, float* %x.addr, align 4 - %0 = load float* %x.addr, align 4 - %sub = fsub float -0.000000e+00, %0 - ret float %sub -} - -define float @baz(float %x) nounwind { -entry: -; CHECK: r{{[0-9]+}} = togglebit(r{{[0-9]+}}, #31) - %x.addr = alloca float, align 4 - store float %x, float* %x.addr, align 4 - %0 = load float* %x.addr, align 4 - %conv = fpext float %0 to double - %mul = fmul double %conv, -1.000000e+00 - %conv1 = fptrunc double %mul to float - ret float %conv1 -} |
