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-rw-r--r--llvm/test/CodeGen/SystemZ/rot-01.ll35
-rw-r--r--llvm/test/CodeGen/SystemZ/shift-11.ll63
2 files changed, 98 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/SystemZ/rot-01.ll b/llvm/test/CodeGen/SystemZ/rot-01.ll
new file mode 100644
index 00000000000..5e97f5d6505
--- /dev/null
+++ b/llvm/test/CodeGen/SystemZ/rot-01.ll
@@ -0,0 +1,35 @@
+; Test shortening of NILL to NILF when the result is used as a rotate amount.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+
+; Test 32-bit rotate.
+define i32 @f1(i32 %val, i32 %amt) {
+; CHECK-LABEL: f1:
+; CHECK: nill %r3, 31
+; CHECK: rll %r2, %r2, 0(%r3)
+ %mod = urem i32 %amt, 32
+
+ %inv = sub i32 32, %mod
+ %parta = shl i32 %val, %mod
+ %partb = lshr i32 %val, %inv
+
+ %rotl = or i32 %parta, %partb
+
+ ret i32 %rotl
+}
+
+; Test 64-bit rotate.
+define i64 @f2(i64 %val, i64 %amt) {
+; CHECK-LABEL: f2:
+; CHECK: nill %r3, 63
+; CHECK: rllg %r2, %r2, 0(%r3)
+ %mod = urem i64 %amt, 64
+
+ %inv = sub i64 64, %mod
+ %parta = shl i64 %val, %mod
+ %partb = lshr i64 %val, %inv
+
+ %rotl = or i64 %parta, %partb
+
+ ret i64 %rotl
+}
diff --git a/llvm/test/CodeGen/SystemZ/shift-11.ll b/llvm/test/CodeGen/SystemZ/shift-11.ll
new file mode 100644
index 00000000000..9741fa5a0b5
--- /dev/null
+++ b/llvm/test/CodeGen/SystemZ/shift-11.ll
@@ -0,0 +1,63 @@
+; Test shortening of NILL to NILF when the result is used as a shift amount.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+
+; Test logical shift right.
+define i32 @f1(i32 %a, i32 %sh) {
+; CHECK-LABEL: f1:
+; CHECK: nill %r3, 31
+; CHECK: srl %r2, 0(%r3)
+ %and = and i32 %sh, 31
+ %shift = lshr i32 %a, %and
+ ret i32 %shift
+}
+
+; Test arithmetic shift right.
+define i32 @f2(i32 %a, i32 %sh) {
+; CHECK-LABEL: f2:
+; CHECK: nill %r3, 31
+; CHECK: sra %r2, 0(%r3)
+ %and = and i32 %sh, 31
+ %shift = ashr i32 %a, %and
+ ret i32 %shift
+}
+
+; Test shift left.
+define i32 @f3(i32 %a, i32 %sh) {
+; CHECK-LABEL: f3:
+; CHECK: nill %r3, 31
+; CHECK: sll %r2, 0(%r3)
+ %and = and i32 %sh, 31
+ %shift = shl i32 %a, %and
+ ret i32 %shift
+}
+
+; Test 64-bit logical shift right.
+define i64 @f4(i64 %a, i64 %sh) {
+; CHECK-LABEL: f4:
+; CHECK: nill %r3, 31
+; CHECK: srlg %r2, %r2, 0(%r3)
+ %and = and i64 %sh, 31
+ %shift = lshr i64 %a, %and
+ ret i64 %shift
+}
+
+; Test 64-bit arithmetic shift right.
+define i64 @f5(i64 %a, i64 %sh) {
+; CHECK-LABEL: f5:
+; CHECK: nill %r3, 31
+; CHECK: srag %r2, %r2, 0(%r3)
+ %and = and i64 %sh, 31
+ %shift = ashr i64 %a, %and
+ ret i64 %shift
+}
+
+; Test 64-bit shift left.
+define i64 @f6(i64 %a, i64 %sh) {
+; CHECK-LABEL: f6:
+; CHECK: nill %r3, 31
+; CHECK: sllg %r2, %r2, 0(%r3)
+ %and = and i64 %sh, 31
+ %shift = shl i64 %a, %and
+ ret i64 %shift
+}
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