6 files changed, 266 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/ARM/reg-alloc-fixed-r6-vla.ll b/llvm/test/CodeGen/ARM/reg-alloc-fixed-r6-vla.ll
new file mode 100644
index 00000000000..0b6fd7443af
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/reg-alloc-fixed-r6-vla.ll
@@ -0,0 +1,44 @@
+; Using VLAs(Variable Length Arrays) in a function will use R6 to keep track
+; of the stack frame, and also spill/restore R6 to the stack.
+; This tests that using -ffixed-r6 (-mattr=+reserve-r6) will stop R6
+; being used and also stop it being spilled/restored to the stack.
+; RUN: llc < %s -mcpu=cortex-m0 -mtriple=thumbv7-arm-none-eabi  | FileCheck %s --check-prefix=CHECK-STATIC --check-prefix=CHECK-R6
+; RUN: llc < %s -mcpu=cortex-m0 -mtriple=thumbv7-arm-none-eabi -mattr=+reserve-r6  | FileCheck %s --check-prefix=CHECK-STATIC --check-prefix=CHECK-NO-R6
+
+define void @f() #0 {
+entry:
+  %i = alloca i32, align 4
+  store i32 0, i32* %i, align 4
+
+  %saved_stack = alloca i8*, align 4
+  %0 = call i8* @llvm.stacksave()
+  store i8* %0, i8** %saved_stack, align 4
+
+  %__vla_expr0 = alloca i32, align 4
+  %1 = load i32, i32* %i, align 4
+  %vla = alloca double, i32 %1, align 8
+  store i32 %1, i32* %__vla_expr0, align 4
+
+  %2 = load i8*, i8** %saved_stack, align 4
+  call void @llvm.stackrestore(i8* %2)
+
+  ret void
+}
+
+declare i8* @llvm.stacksave() #1
+declare void @llvm.stackrestore(i8* %ptr) #1
+
+attributes #0 = { noinline nounwind "stackrealign" }
+attributes #1 = { nounwind }
+
+; CHECK-STATIC: push {r4,
+; CHECK-R6: r6
+; CHECK-NO-R6-NOT: r6
+; CHECK-STATIC: lr}
+; CHECK-R6: r6
+; CHECK-NO-R6-NOT: r6
+; CHECK-STATIC: pop {r4,
+; CHECK-R6: r6
+; CHECK-NO-R6-NOT: r6
+; CHECK-STATIC: pc}
+
diff --git a/llvm/test/CodeGen/ARM/reg-alloc-with-fixed-reg-r6-modified.ll b/llvm/test/CodeGen/ARM/reg-alloc-with-fixed-reg-r6-modified.ll
new file mode 100644
index 00000000000..e2a4af87dde
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/reg-alloc-with-fixed-reg-r6-modified.ll
@@ -0,0 +1,63 @@
+; RUN: llc < %s -mattr=+reserve-r6 -mtriple=arm-linux-gnueabi -O0 -filetype=asm --regalloc=fast 2>&1 | FileCheck %s
+;
+; Equivalent C source code
+; register unsigned r6 asm("r6");
+; void bar(unsigned int i,
+;          unsigned int j,
+;          unsigned int k,
+;          unsigned int l,
+;          unsigned int m,
+;          unsigned int n,
+;          unsigned int o,
+;          unsigned int p)
+; {
+;     r6 = 10;
+;     unsigned int result = i + j + k + l + m + n + o + p;
+; }
+declare void @llvm.write_register.i32(metadata, i32) nounwind
+
+define void @bar(i32 %i, i32 %j, i32 %k, i32 %l, i32 %m, i32 %n, i32 %o, i32 %p) nounwind {
+entry:
+; CHECK-NOT: push {{{.*}}r6,{{.*}}}
+; CHECK: {{.*}}mov{{.*}}r6,{{.*}}
+; CHECK-NOT: {{.*}}r6{{.*}}
+  %i.addr = alloca i32, align 4
+  %j.addr = alloca i32, align 4
+  %k.addr = alloca i32, align 4
+  %l.addr = alloca i32, align 4
+  %m.addr = alloca i32, align 4
+  %n.addr = alloca i32, align 4
+  %o.addr = alloca i32, align 4
+  %p.addr = alloca i32, align 4
+  %result = alloca i32, align 4
+  store i32 %i, i32* %i.addr, align 4
+  store i32 %j, i32* %j.addr, align 4
+  store i32 %k, i32* %k.addr, align 4
+  store i32 %l, i32* %l.addr, align 4
+  store i32 %m, i32* %m.addr, align 4
+  store i32 %n, i32* %n.addr, align 4
+  store i32 %o, i32* %o.addr, align 4
+  store i32 %p, i32* %p.addr, align 4
+  call void @llvm.write_register.i32(metadata !0, i32 10)
+  %0 = load i32, i32* %i.addr, align 4
+  %1 = load i32, i32* %j.addr, align 4
+  %add = add i32 %0, %1
+  %2 = load i32, i32* %k.addr, align 4
+  %add1 = add i32 %add, %2
+  %3 = load i32, i32* %l.addr, align 4
+  %add2 = add i32 %add1, %3
+  %4 = load i32, i32* %m.addr, align 4
+  %add3 = add i32 %add2, %4
+  %5 = load i32, i32* %n.addr, align 4
+  %add4 = add i32 %add3, %5
+  %6 = load i32, i32* %o.addr, align 4
+  %add5 = add i32 %add4, %6
+  %7 = load i32, i32* %p.addr, align 4
+  %add6 = add i32 %add5, %7
+  store i32 %add6, i32* %result, align 4
+  ret void
+}
+
+!llvm.named.register.r6 = !{!0}
+!0 = !{!"r6"}
+
diff --git a/llvm/test/CodeGen/ARM/reg-alloc-with-fixed-reg-r6.ll b/llvm/test/CodeGen/ARM/reg-alloc-with-fixed-reg-r6.ll
new file mode 100644
index 00000000000..3647c0701a7
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/reg-alloc-with-fixed-reg-r6.ll
@@ -0,0 +1,57 @@
+; RUN: llc < %s -mattr=+reserve-r6 -mtriple=arm-linux-gnueabi -O0 -filetype=asm --regalloc=fast 2>&1 | FileCheck %s
+;
+; Equivalent C source code
+; void bar(unsigned int i,
+;          unsigned int j,
+;          unsigned int k,
+;          unsigned int l,
+;          unsigned int m,
+;          unsigned int n,
+;          unsigned int o,
+;          unsigned int p)
+; {
+;     unsigned int result = i + j + k + l + m + n + o + p;
+; }
+
+define void @bar(i32 %i, i32 %j, i32 %k, i32 %l, i32 %m, i32 %n, i32 %o, i32 %p) nounwind {
+entry:
+; CHECK-NOT: push {{{.*}}r6,{{.*}}}
+  %i.addr = alloca i32, align 4
+  %j.addr = alloca i32, align 4
+  %k.addr = alloca i32, align 4
+  %l.addr = alloca i32, align 4
+  %m.addr = alloca i32, align 4
+  %n.addr = alloca i32, align 4
+  %o.addr = alloca i32, align 4
+  %p.addr = alloca i32, align 4
+  %result = alloca i32, align 4
+  store i32 %i, i32* %i.addr, align 4
+  store i32 %j, i32* %j.addr, align 4
+  store i32 %k, i32* %k.addr, align 4
+  store i32 %l, i32* %l.addr, align 4
+  store i32 %m, i32* %m.addr, align 4
+  store i32 %n, i32* %n.addr, align 4
+  store i32 %o, i32* %o.addr, align 4
+  store i32 %p, i32* %p.addr, align 4
+  %0 = load i32, i32* %i.addr, align 4
+  %1 = load i32, i32* %j.addr, align 4
+  %add = add i32 %0, %1
+  %2 = load i32, i32* %k.addr, align 4
+  %add1 = add i32 %add, %2
+  %3 = load i32, i32* %l.addr, align 4
+  %add2 = add i32 %add1, %3
+  %4 = load i32, i32* %m.addr, align 4
+  %add3 = add i32 %add2, %4
+  %5 = load i32, i32* %n.addr, align 4
+  %add4 = add i32 %add3, %5
+  %6 = load i32, i32* %o.addr, align 4
+  %add5 = add i32 %add4, %6
+  %7 = load i32, i32* %p.addr, align 4
+  %add6 = add i32 %add5, %7
+  store i32 %add6, i32* %result, align 4
+; CHECK: {{.*}}r5{{.*}}
+; CHECK-NOT: {{.*}}r6{{.*}}
+  ret void
+; CHECK-NOT: pop {{{.*}}r6,{{.*}}}
+}
+
diff --git a/llvm/test/CodeGen/ARM/reg-alloc-wout-fixed-regs.ll b/llvm/test/CodeGen/ARM/reg-alloc-wout-fixed-regs.ll
new file mode 100644
index 00000000000..d1f020936a3
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/reg-alloc-wout-fixed-regs.ll
@@ -0,0 +1,58 @@
+; RUN: llc < %s -mtriple=arm-linux-gnueabi  -O0 -filetype=asm --regalloc=fast 2>&1 | FileCheck %s
+;
+; Equivalent C source code
+; void bar(unsigned int i,
+;          unsigned int j,
+;          unsigned int k,
+;          unsigned int l,
+;          unsigned int m,
+;          unsigned int n,
+;          unsigned int o,
+;          unsigned int p)
+; {
+;     unsigned int result = i + j + k + l + m + n + o + p;
+; }
+
+define void @bar(i32 %i, i32 %j, i32 %k, i32 %l, i32 %m, i32 %n, i32 %o, i32 %p) nounwind {
+entry:
+; CHECK: push {{{.*}}r4, r5{{.*}}}
+  %i.addr = alloca i32, align 4
+  %j.addr = alloca i32, align 4
+  %k.addr = alloca i32, align 4
+  %l.addr = alloca i32, align 4
+  %m.addr = alloca i32, align 4
+  %n.addr = alloca i32, align 4
+  %o.addr = alloca i32, align 4
+  %p.addr = alloca i32, align 4
+  %result = alloca i32, align 4
+  store i32 %i, i32* %i.addr, align 4
+  store i32 %j, i32* %j.addr, align 4
+  store i32 %k, i32* %k.addr, align 4
+  store i32 %l, i32* %l.addr, align 4
+  store i32 %m, i32* %m.addr, align 4
+  store i32 %n, i32* %n.addr, align 4
+  store i32 %o, i32* %o.addr, align 4
+  store i32 %p, i32* %p.addr, align 4
+  %0 = load i32, i32* %i.addr, align 4
+  %1 = load i32, i32* %j.addr, align 4
+  %add = add i32 %0, %1
+  %2 = load i32, i32* %k.addr, align 4
+  %add1 = add i32 %add, %2
+  %3 = load i32, i32* %l.addr, align 4
+  %add2 = add i32 %add1, %3
+  %4 = load i32, i32* %m.addr, align 4
+  %add3 = add i32 %add2, %4
+  %5 = load i32, i32* %n.addr, align 4
+  %add4 = add i32 %add3, %5
+  %6 = load i32, i32* %o.addr, align 4
+  %add5 = add i32 %add4, %6
+  %7 = load i32, i32* %p.addr, align 4
+  %add6 = add i32 %add5, %7
+  store i32 %add6, i32* %result, align 4
+; CHECK: {{.*}}r4{{.*}}
+; CHECK: {{.*}}r5{{.*}}
+
+; CHECK: pop {{{.*}}r4, r5{{.*}}}
+  ret void
+}
+
diff --git a/llvm/test/CodeGen/Thumb/callee_save_reserved.ll b/llvm/test/CodeGen/Thumb/callee_save_reserved.ll
new file mode 100644
index 00000000000..0329d7886a2
--- /dev/null
+++ b/llvm/test/CodeGen/Thumb/callee_save_reserved.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s -mtriple=thumbv6m-none-eabi -verify-machineinstrs -frame-pointer=none -mattr=+reserve-r6,+reserve-r8 \
+; RUN:     -asm-verbose=false | FileCheck --check-prefix=CHECK-INVALID %s
+
+; Reserved low registers should not be used to correct reg deficit.
+define <4 x i32> @four_high_four_return_reserved() {
+entry:
+  ; CHECK-INVALID-NOT: r{{6|8}}
+  tail call void asm sideeffect "", "~{r8},~{r9}"()
+  %vecinit = insertelement <4 x i32> undef, i32 1, i32 0
+  %vecinit11 = insertelement <4 x i32> %vecinit, i32 2, i32 1
+  %vecinit12 = insertelement <4 x i32> %vecinit11, i32 3, i32 2
+  %vecinit13 = insertelement <4 x i32> %vecinit12, i32 4, i32 3
+  ret <4 x i32> %vecinit13
+}
+
diff --git a/llvm/test/Feature/reserve_global_reg.ll b/llvm/test/Feature/reserve_global_reg.ll
new file mode 100644
index 00000000000..06081cae1fb
--- /dev/null
+++ b/llvm/test/Feature/reserve_global_reg.ll
@@ -0,0 +1,29 @@
+; RUN: not llc < %s -mtriple=thumbv7-apple-darwin -mattr=+reserve-r7 -o - 2>&1 | FileCheck -check-prefix=CHECK-RESERVE-FP7 %s
+; RUN: not llc < %s -mtriple=armv7-windows-msvc -mattr=+reserve-r11 -o - 2>&1 | FileCheck -check-prefix=CHECK-RESERVE-FP11 %s
+; RUN: not llc < %s -mtriple=thumbv7-windows -mattr=+reserve-r11 -o - 2>&1 | FileCheck -check-prefix=CHECK-RESERVE-FP11-2 %s
+
+; int test(int a, int b, int c) {
+;   return a + b + c;
+; }
+
+; Function Attrs: noinline nounwind optnone
+define hidden i32 @_Z4testiii(i32 %a, i32 %b, i32 %c) #0 {
+entry:
+  %a.addr = alloca i32, align 4
+  %b.addr = alloca i32, align 4
+  %c.addr = alloca i32, align 4
+  store i32 %a, i32* %a.addr, align 4
+  store i32 %b, i32* %b.addr, align 4
+  store i32 %c, i32* %c.addr, align 4
+  %0 = load i32, i32* %a.addr, align 4
+  %1 = load i32, i32* %b.addr, align 4
+  %add = add nsw i32 %0, %1
+  %2 = load i32, i32* %c.addr, align 4
+  %add1 = add nsw i32 %add, %2
+  ret i32 %add1
+}
+
+; CHECK-RESERVE-FP7: Register r7 has been specified but is used as the frame pointer for this target.
+; CHECK-RESERVE-FP11: Register r11 has been specified but is used as the frame pointer for this target.
+; CHECK-RESERVE-FP11-2: Register r11 has been specified but is used as the frame pointer for this target.
+