diff options
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/CodeGen/Mips/2013-11-18-fp64-const0.ll | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Mips/Fast-ISel/simplestorefp1.ll | 6 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Mips/buildpairextractelementf64.ll | 4 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Mips/fcopysign.ll | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Mips/fmadd1.ll | 16 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Mips/mno-ldc1-sdc1.ll | 4 |
6 files changed, 17 insertions, 17 deletions
diff --git a/llvm/test/CodeGen/Mips/2013-11-18-fp64-const0.ll b/llvm/test/CodeGen/Mips/2013-11-18-fp64-const0.ll index f8390d9a1ca..6a210a0c76c 100644 --- a/llvm/test/CodeGen/Mips/2013-11-18-fp64-const0.ll +++ b/llvm/test/CodeGen/Mips/2013-11-18-fp64-const0.ll @@ -1,5 +1,5 @@ ; RUN: llc -march=mips -mattr=-fp64 < %s | FileCheck -check-prefix=CHECK-FP32 %s -; RUN: llc -march=mips -mattr=+fp64 < %s | FileCheck -check-prefix=CHECK-FP64 %s +; RUN: llc -march=mips -mcpu=mips32r2 -mattr=+fp64 < %s | FileCheck -check-prefix=CHECK-FP64 %s ; This test case is a simplified version of an llvm-stress generated test with ; seed=3718491962. diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/simplestorefp1.ll b/llvm/test/CodeGen/Mips/Fast-ISel/simplestorefp1.ll index a374470d896..6759c01c774 100644 --- a/llvm/test/CodeGen/Mips/Fast-ISel/simplestorefp1.ll +++ b/llvm/test/CodeGen/Mips/Fast-ISel/simplestorefp1.ll @@ -28,9 +28,9 @@ entry: ; CHECK: ori $[[REG2a:[0-9]+]], $[[REG1a]], 49353 ; CHECK: lui $[[REG1b:[0-9]+]], 21403 ; CHECK: ori $[[REG2b:[0-9]+]], $[[REG1b]], 34951 -; CHECK: mtc1 $[[REG2b]], $f[[REG3b:[0-9]+]] -; CHECK: mtc1 $[[REG2a]], $f[[REG3a:[0-9]+]] -; CHECK: sdc1 $f[[REG3b]], 0(${{[0-9]+}}) +; CHECK: mtc1 $[[REG2b]], $f[[REG3:[0-9]+]] +; CHECK: mthc1 $[[REG2a]], $f[[REG3]] +; CHECK: sdc1 $f[[REG3]], 0(${{[0-9]+}}) ; CHECK: .end d1 ret void } diff --git a/llvm/test/CodeGen/Mips/buildpairextractelementf64.ll b/llvm/test/CodeGen/Mips/buildpairextractelementf64.ll index b9bf2b60a66..88d1d07e29a 100644 --- a/llvm/test/CodeGen/Mips/buildpairextractelementf64.ll +++ b/llvm/test/CodeGen/Mips/buildpairextractelementf64.ll @@ -1,7 +1,7 @@ ; RUN: llc -march=mipsel < %s | FileCheck %s -check-prefix=FP32 -check-prefix=CHECK ; RUN: llc -march=mips < %s | FileCheck %s -check-prefix=FP32 -check-prefix=CHECK -; RUN: llc -march=mipsel -mattr=+fp64 < %s | FileCheck %s -check-prefix=FP64 -check-prefix=CHECK -; RUN: llc -march=mips -mattr=+fp64 < %s | FileCheck %s -check-prefix=FP64 -check-prefix=CHECK +; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+fp64 < %s | FileCheck %s -check-prefix=FP64 -check-prefix=CHECK +; RUN: llc -march=mips -mcpu=mips32r2 -mattr=+fp64 < %s | FileCheck %s -check-prefix=FP64 -check-prefix=CHECK @a = external global i32 diff --git a/llvm/test/CodeGen/Mips/fcopysign.ll b/llvm/test/CodeGen/Mips/fcopysign.ll index 44c4117510b..3a9d9c73b27 100644 --- a/llvm/test/CodeGen/Mips/fcopysign.ll +++ b/llvm/test/CodeGen/Mips/fcopysign.ll @@ -17,7 +17,7 @@ entry: ; 32R2: ext $[[EXT:[0-9]+]], ${{[0-9]+}}, 31, 1 ; 32R2: ins $[[INS:[0-9]+]], $[[EXT]], 31, 1 -; 32R2: mtc1 $[[INS]], $f1 +; 32R2: mthc1 $[[INS]], $f0 ; 64: daddiu $[[T0:[0-9]+]], $zero, 1 ; 64: dsll $[[MSK1:[0-9]+]], $[[T0]], 63 diff --git a/llvm/test/CodeGen/Mips/fmadd1.ll b/llvm/test/CodeGen/Mips/fmadd1.ll index bd672ef4b00..271631efb40 100644 --- a/llvm/test/CodeGen/Mips/fmadd1.ll +++ b/llvm/test/CodeGen/Mips/fmadd1.ll @@ -196,8 +196,8 @@ entry: ; 32R2: ldc1 $[[T0:f[0-9]+]], 16($sp) ; 32R2: madd.d $[[T1:f[0-9]+]], $[[T0]], $f12, $f14 -; 32R2: mtc1 $zero, $[[T2:f[02468]+]] -; 32R2: mtc1 $zero, ${{f[13579]+}} +; 32R2: mtc1 $zero, $[[T2:f[0-9]+]] +; 32R2: mthc1 $zero, $[[T2]] ; 32R2: add.d $f0, $[[T1]], $[[T2]] ; 32R6-DAG: ldc1 $[[T0:f[0-9]+]], 16($sp) @@ -238,8 +238,8 @@ entry: ; 32R2: ldc1 $[[T0:f[0-9]+]], 16($sp) ; 32R2: msub.d $[[T1:f[0-9]+]], $[[T0]], $f12, $f14 -; 32R2: mtc1 $zero, $[[T2:f[02468]+]] -; 32R2: mtc1 $zero, ${{f[13579]+}} +; 32R2: mtc1 $zero, $[[T2:f[0-9]+]] +; 32R2: mthc1 $zero, $[[T2]] ; 32R2: add.d $f0, $[[T1]], $[[T2]] ; 32R6-DAG: ldc1 $[[T0:f[0-9]+]], 16($sp) @@ -283,8 +283,8 @@ entry: ; 32R2-NAN: ldc1 $[[T0:f[0-9]+]], 16($sp) ; 32R2-NAN: madd.d $[[T1:f[0-9]+]], $[[T0]], $f12, $f14 -; 32R2-NAN: mtc1 $zero, $[[T2:f[02468]+]] -; 32R2-NAN: mtc1 $zero, ${{f[13579]+}} +; 32R2-NAN: mtc1 $zero, $[[T2:f[0-9]+]] +; 32R2-NAN: mthc1 $zero, $[[T2]] ; 32R2-NAN: sub.d $f0, $[[T2]], $[[T1]] ; 32R6-DAG: ldc1 $[[T0:f[0-9]+]], 16($sp) @@ -330,8 +330,8 @@ entry: ; 32R2-NAN: ldc1 $[[T0:f[0-9]+]], 16($sp) ; 32R2-NAN: msub.d $[[T1:f[0-9]+]], $[[T0]], $f12, $f14 -; 32R2-NAN: mtc1 $zero, $[[T2:f[02468]+]] -; 32R2-NAN: mtc1 $zero, ${{f[13579]+}} +; 32R2-NAN: mtc1 $zero, $[[T2:f[0-9]+]] +; 32R2-NAN: mthc1 $zero, $[[T2]] ; 32R2-NAN: sub.d $f0, $[[T2]], $[[T1]] ; 32R6-DAG: ldc1 $[[T0:f[0-9]+]], 16($sp) diff --git a/llvm/test/CodeGen/Mips/mno-ldc1-sdc1.ll b/llvm/test/CodeGen/Mips/mno-ldc1-sdc1.ll index f4854f88054..ffc977a1825 100644 --- a/llvm/test/CodeGen/Mips/mno-ldc1-sdc1.ll +++ b/llvm/test/CodeGen/Mips/mno-ldc1-sdc1.ll @@ -13,7 +13,7 @@ ; LE-PIC-DAG: lw $[[R0:[0-9]+]], 0(${{[0-9]+}}) ; LE-PIC-DAG: lw $[[R1:[0-9]+]], 4(${{[0-9]+}}) ; LE-PIC-DAG: mtc1 $[[R0]], $f0 -; LE-PIC-DAG: mtc1 $[[R1]], $f1 +; LE-PIC-DAG: mthc1 $[[R1]], $f0 ; LE-STATIC-LABEL: test_ldc1: ; LE-STATIC-DAG: lui $[[R0:[0-9]+]], %hi(g0) ; LE-STATIC-DAG: lw $[[R1:[0-9]+]], %lo(g0)($[[R0]]) @@ -66,7 +66,7 @@ entry: ; LE-PIC-DAG: lw $[[R0:[0-9]+]], 0(${{[0-9]+}}) ; LE-PIC-DAG: lw $[[R1:[0-9]+]], 4(${{[0-9]+}}) ; LE-PIC-DAG: mtc1 $[[R0]], $f0 -; LE-PIC-DAG: mtc1 $[[R1]], $f1 +; LE-PIC-DAG: mthc1 $[[R1]], $f0 ; CHECK-LDC1-SDC1-LABEL: test_ldxc1: ; CHECK-LDC1-SDC1: ldxc1 $f{{[0-9]+}} |
