diff options
Diffstat (limited to 'llvm/test')
19 files changed, 8 insertions, 59 deletions
diff --git a/llvm/test/CodeGen/AArch64/ldst-opt-dbg-limit.mir b/llvm/test/CodeGen/AArch64/ldst-opt-dbg-limit.mir index 65d8acb3578..88a4b2c0cd9 100644 --- a/llvm/test/CodeGen/AArch64/ldst-opt-dbg-limit.mir +++ b/llvm/test/CodeGen/AArch64/ldst-opt-dbg-limit.mir @@ -28,7 +28,6 @@ name: promote-load-from-store alignment: 2 exposesReturnsTwice: false -allVRegsAllocated: true tracksRegLiveness: false liveins: - { reg: '%x0' } @@ -83,7 +82,6 @@ body: | name: store-pair alignment: 2 exposesReturnsTwice: false -allVRegsAllocated: true tracksRegLiveness: false liveins: - { reg: '%x0' } diff --git a/llvm/test/CodeGen/AArch64/movimm-wzr.mir b/llvm/test/CodeGen/AArch64/movimm-wzr.mir index c26643ed106..c6bfcf121a3 100644 --- a/llvm/test/CodeGen/AArch64/movimm-wzr.mir +++ b/llvm/test/CodeGen/AArch64/movimm-wzr.mir @@ -15,7 +15,6 @@ name: test_mov_0 alignment: 2 exposesReturnsTwice: false -allVRegsAllocated: true tracksRegLiveness: false frameInfo: isFrameAddressTaken: false diff --git a/llvm/test/CodeGen/ARM/ARMLoadStoreDBG.mir b/llvm/test/CodeGen/ARM/ARMLoadStoreDBG.mir index 144961b7ac9..0e6f80bfb48 100644 --- a/llvm/test/CodeGen/ARM/ARMLoadStoreDBG.mir +++ b/llvm/test/CodeGen/ARM/ARMLoadStoreDBG.mir @@ -79,7 +79,6 @@ name: f alignment: 1 exposesReturnsTwice: false -allVRegsAllocated: true tracksRegLiveness: true liveins: - { reg: '%r0' } diff --git a/llvm/test/CodeGen/Hexagon/ifcvt-impuse-livein.mir b/llvm/test/CodeGen/Hexagon/ifcvt-impuse-livein.mir index 83a1046357c..780b9cedf7f 100644 --- a/llvm/test/CodeGen/Hexagon/ifcvt-impuse-livein.mir +++ b/llvm/test/CodeGen/Hexagon/ifcvt-impuse-livein.mir @@ -14,7 +14,6 @@ --- name: foo tracksRegLiveness: true -allVRegsAllocated: true body: | bb.0: successors: %bb.1, %bb.2 diff --git a/llvm/test/CodeGen/MIR/AArch64/inst-size-tlsdesc-callseq.mir b/llvm/test/CodeGen/MIR/AArch64/inst-size-tlsdesc-callseq.mir index 0ad0e9d568b..7e7b318009a 100644 --- a/llvm/test/CodeGen/MIR/AArch64/inst-size-tlsdesc-callseq.mir +++ b/llvm/test/CodeGen/MIR/AArch64/inst-size-tlsdesc-callseq.mir @@ -33,7 +33,6 @@ name: test_tlsdesc_callseq_length alignment: 2 exposesReturnsTwice: false -allVRegsAllocated: true tracksRegLiveness: false liveins: - { reg: '%w0' } diff --git a/llvm/test/CodeGen/MIR/AArch64/machine-dead-copy.mir b/llvm/test/CodeGen/MIR/AArch64/machine-dead-copy.mir index 90f2f3c0999..cb552e5cab3 100644 --- a/llvm/test/CodeGen/MIR/AArch64/machine-dead-copy.mir +++ b/llvm/test/CodeGen/MIR/AArch64/machine-dead-copy.mir @@ -13,9 +13,8 @@ # CHECK-LABEL: name: copyprop1 # CHECK: bb.0: # CHECK-NOT: %w20 = COPY -name: copyprop1 -allVRegsAllocated: true -body: | +name: copyprop1 +body: | bb.0: liveins: %w0, %w1 %w20 = COPY %w1 @@ -28,9 +27,8 @@ body: | # CHECK-LABEL: name: copyprop2 # CHECK: bb.0: # CHECK: %w20 = COPY -name: copyprop2 -allVRegsAllocated: true -body: | +name: copyprop2 +body: | bb.0: liveins: %w0, %w1 %w20 = COPY %w1 @@ -43,9 +41,8 @@ body: | # CHECK-LABEL: name: copyprop3 # CHECK: bb.0: # CHECK-NOT: COPY -name: copyprop3 -allVRegsAllocated: true -body: | +name: copyprop3 +body: | bb.0: liveins: %w0, %w1 %w20 = COPY %w1 @@ -58,9 +55,8 @@ body: | # CHECK-LABEL: name: copyprop4 # CHECK: bb.0: # CHECK-NOT: COPY -name: copyprop4 -allVRegsAllocated: true -body: | +name: copyprop4 +body: | bb.0: liveins: %w0, %w1 %w20 = COPY %w0 diff --git a/llvm/test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir b/llvm/test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir index 7a0d2989d56..74ea7c63d4b 100644 --- a/llvm/test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir +++ b/llvm/test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir @@ -90,7 +90,6 @@ name: f alignment: 1 exposesReturnsTwice: false -allVRegsAllocated: true tracksRegLiveness: true liveins: - { reg: '%r0' } diff --git a/llvm/test/CodeGen/MIR/Hexagon/anti-dep-partial.mir b/llvm/test/CodeGen/MIR/Hexagon/anti-dep-partial.mir index a83c53e57cd..09bc49c508a 100644 --- a/llvm/test/CodeGen/MIR/Hexagon/anti-dep-partial.mir +++ b/llvm/test/CodeGen/MIR/Hexagon/anti-dep-partial.mir @@ -10,7 +10,6 @@ --- name: foo tracksRegLiveness: true -allVRegsAllocated: true body: | bb.0: successors: diff --git a/llvm/test/CodeGen/MIR/Lanai/peephole-compare.mir b/llvm/test/CodeGen/MIR/Lanai/peephole-compare.mir index e9f2966688c..5056a05ed1f 100644 --- a/llvm/test/CodeGen/MIR/Lanai/peephole-compare.mir +++ b/llvm/test/CodeGen/MIR/Lanai/peephole-compare.mir @@ -175,7 +175,6 @@ name: test0a alignment: 2 exposesReturnsTwice: false -allVRegsAllocated: false tracksRegLiveness: true registers: - { id: 0, class: gpr } @@ -220,7 +219,6 @@ body: | name: test0b alignment: 2 exposesReturnsTwice: false -allVRegsAllocated: false tracksRegLiveness: true registers: - { id: 0, class: gpr } @@ -263,7 +261,6 @@ body: | name: test1a alignment: 2 exposesReturnsTwice: false -allVRegsAllocated: false tracksRegLiveness: true registers: - { id: 0, class: gpr } @@ -310,7 +307,6 @@ body: | name: test1b alignment: 2 exposesReturnsTwice: false -allVRegsAllocated: false tracksRegLiveness: true registers: - { id: 0, class: gpr } @@ -357,7 +353,6 @@ body: | name: test2a alignment: 2 exposesReturnsTwice: false -allVRegsAllocated: false tracksRegLiveness: true registers: - { id: 0, class: gpr } @@ -404,7 +399,6 @@ body: | name: test2b alignment: 2 exposesReturnsTwice: false -allVRegsAllocated: false tracksRegLiveness: true registers: - { id: 0, class: gpr } @@ -451,7 +445,6 @@ body: | name: test3 alignment: 2 exposesReturnsTwice: false -allVRegsAllocated: false tracksRegLiveness: true registers: - { id: 0, class: gpr } @@ -498,7 +491,6 @@ body: | name: test4 alignment: 2 exposesReturnsTwice: false -allVRegsAllocated: false tracksRegLiveness: true registers: - { id: 0, class: gpr } @@ -609,7 +601,6 @@ body: | name: testBB alignment: 2 exposesReturnsTwice: false -allVRegsAllocated: false tracksRegLiveness: true registers: - { id: 0, class: gpr } diff --git a/llvm/test/CodeGen/PowerPC/aantidep-def-ec.mir b/llvm/test/CodeGen/PowerPC/aantidep-def-ec.mir index a49251bde35..cf6ab35d8db 100644 --- a/llvm/test/CodeGen/PowerPC/aantidep-def-ec.mir +++ b/llvm/test/CodeGen/PowerPC/aantidep-def-ec.mir @@ -44,7 +44,6 @@ name: mm_update_next_owner alignment: 4 exposesReturnsTwice: false -allVRegsAllocated: true tracksRegLiveness: true liveins: - { reg: '%x3' } diff --git a/llvm/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir b/llvm/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir index 45ff51dc958..bd0e7383d52 100644 --- a/llvm/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir +++ b/llvm/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir @@ -26,7 +26,6 @@ name: test1 alignment: 4 exposesReturnsTwice: false -allVRegsAllocated: true tracksRegLiveness: true frameInfo: isFrameAddressTaken: false diff --git a/llvm/test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir b/llvm/test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir index d4b83b9a499..bba3e152699 100644 --- a/llvm/test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir +++ b/llvm/test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir @@ -32,7 +32,6 @@ name: fn1 alignment: 2 exposesReturnsTwice: false -allVRegsAllocated: false tracksRegLiveness: true registers: - { id: 0, class: g8rc } diff --git a/llvm/test/CodeGen/X86/eflags-copy-expansion.mir b/llvm/test/CodeGen/X86/eflags-copy-expansion.mir index 43d4e3b7f57..36044b4d205 100644 --- a/llvm/test/CodeGen/X86/eflags-copy-expansion.mir +++ b/llvm/test/CodeGen/X86/eflags-copy-expansion.mir @@ -19,7 +19,6 @@ --- name: foo -allVRegsAllocated: true tracksRegLiveness: true liveins: - { reg: '%edi' } diff --git a/llvm/test/CodeGen/X86/fixup-bw-copy.mir b/llvm/test/CodeGen/X86/fixup-bw-copy.mir index e39688fe7db..bbb60ad4b59 100644 --- a/llvm/test/CodeGen/X86/fixup-bw-copy.mir +++ b/llvm/test/CodeGen/X86/fixup-bw-copy.mir @@ -38,7 +38,6 @@ --- name: test_movb_killed -allVRegsAllocated: true tracksRegLiveness: true liveins: - { reg: '%edi' } @@ -54,7 +53,6 @@ body: | --- name: test_movb_impuse -allVRegsAllocated: true tracksRegLiveness: true liveins: - { reg: '%edi' } @@ -70,7 +68,6 @@ body: | --- name: test_movb_impdef_gr64 -allVRegsAllocated: true tracksRegLiveness: true liveins: - { reg: '%edi' } @@ -86,7 +83,6 @@ body: | --- name: test_movb_impdef_gr32 -allVRegsAllocated: true tracksRegLiveness: true liveins: - { reg: '%edi' } @@ -102,7 +98,6 @@ body: | --- name: test_movb_impdef_gr16 -allVRegsAllocated: true tracksRegLiveness: true liveins: - { reg: '%edi' } @@ -118,7 +113,6 @@ body: | --- name: test_movw_impdef_gr32 -allVRegsAllocated: true tracksRegLiveness: true liveins: - { reg: '%edi' } @@ -134,7 +128,6 @@ body: | --- name: test_movw_impdef_gr64 -allVRegsAllocated: true tracksRegLiveness: true liveins: - { reg: '%edi' } diff --git a/llvm/test/CodeGen/X86/implicit-null-checks.mir b/llvm/test/CodeGen/X86/implicit-null-checks.mir index b2b7acaf5da..16a1a1ca2dc 100644 --- a/llvm/test/CodeGen/X86/implicit-null-checks.mir +++ b/llvm/test/CodeGen/X86/implicit-null-checks.mir @@ -85,7 +85,6 @@ name: imp_null_check_with_bitwise_op_0 # CHECK-LABEL: name: imp_null_check_with_bitwise_op_0 alignment: 4 -allVRegsAllocated: true tracksRegLiveness: true liveins: - { reg: '%rdi' } @@ -128,7 +127,6 @@ body: | --- name: imp_null_check_with_bitwise_op_1 alignment: 4 -allVRegsAllocated: true tracksRegLiveness: true liveins: - { reg: '%rdi' } @@ -176,7 +174,6 @@ body: | name: imp_null_check_with_bitwise_op_2 # CHECK-LABEL: name: imp_null_check_with_bitwise_op_2 alignment: 4 -allVRegsAllocated: true tracksRegLiveness: true liveins: - { reg: '%rdi' } @@ -220,7 +217,6 @@ body: | name: imp_null_check_with_bitwise_op_3 # CHECK-LABEL: name: imp_null_check_with_bitwise_op_3 alignment: 4 -allVRegsAllocated: true tracksRegLiveness: true liveins: - { reg: '%rdi' } diff --git a/llvm/test/CodeGen/X86/machine-copy-prop.mir b/llvm/test/CodeGen/X86/machine-copy-prop.mir index c2cb4ceb7fb..225a43061c9 100644 --- a/llvm/test/CodeGen/X86/machine-copy-prop.mir +++ b/llvm/test/CodeGen/X86/machine-copy-prop.mir @@ -25,7 +25,6 @@ # CHECK-NOT: COPY # CHECK-NEXT: NOOP implicit %rax, implicit %rdi name: copyprop_remove_kill0 -allVRegsAllocated: true body: | bb.0: %rax = COPY %rdi @@ -43,7 +42,6 @@ body: | # CHECK-NOT: COPY # CHECK-NEXT: NOOP implicit %rax, implicit %rdi name: copyprop_remove_kill1 -allVRegsAllocated: true body: | bb.0: %rax = COPY %rdi @@ -61,7 +59,6 @@ body: | # CHECK-NOT: COPY # CHECK-NEXT: NOOP implicit %rax, implicit %rdi name: copyprop_remove_kill2 -allVRegsAllocated: true body: | bb.0: %ax = COPY %di @@ -79,7 +76,6 @@ body: | # CHECK-NOT: COPY # CHECK-NEXT: NOOP implicit %rax, implicit %rdi name: copyprop0 -allVRegsAllocated: true body: | bb.0: %rax = COPY %rdi @@ -96,7 +92,6 @@ body: | # CHECK-NEXT: NOOP implicit %rax # CHECK-NEXT: NOOP implicit %rax, implicit %rdi name: copyprop1 -allVRegsAllocated: true body: | bb.0: %rax = COPY %rdi @@ -113,7 +108,6 @@ body: | # CHECK-NOT: %rax = COPY %rdi # CHECK-NEXT: NOOP implicit %rax, implicit %rdi name: copyprop2 -allVRegsAllocated: true body: | bb.0: %rax = COPY %rdi @@ -132,7 +126,6 @@ body: | # CHECK-NEXT: %rbp = COPY %rax # CHECK-NEXT: NOOP implicit %rax, implicit %rbp name: nocopyprop0 -allVRegsAllocated: true body: | bb.0: %rax = COPY %rbp @@ -150,7 +143,6 @@ body: | # CHECK-NEXT: %rax = COPY %rbp # CHECK-NEXT: NOOP implicit %rax, implicit %rbp name: nocopyprop1 -allVRegsAllocated: true body: | bb.0: %rbp = COPY %rax @@ -168,7 +160,6 @@ body: | # CHECK-NEXT: %rax = COPY %rbp # CHECK-NEXT: NOOP implicit %rax, implicit %rbp name: nocopyprop2 -allVRegsAllocated: true body: | bb.0: %rax = COPY %rbp @@ -186,7 +177,6 @@ body: | # CHECK-NEXT: %rbp = COPY %rax # CHECK-NEXT: NOOP implicit %rax, implicit %rbp name: nocopyprop3 -allVRegsAllocated: true body: | bb.0: %rbp = COPY %rax @@ -203,7 +193,6 @@ body: | # CHECK-NEXT: %rax = COPY %rip # CHECK-NEXT: NOOP implicit %rax name: nocopyprop4 -allVRegsAllocated: true body: | bb.0: %rax = COPY %rip @@ -219,7 +208,6 @@ body: | # CHECK-NEXT: %rip = COPY %rax # CHECK-NEXT: %rip = COPY %rax name: nocopyprop5 -allVRegsAllocated: true body: | bb.0: %rip = COPY %rax diff --git a/llvm/test/CodeGen/X86/pr27681.mir b/llvm/test/CodeGen/X86/pr27681.mir index 9473a21d732..3e931b182e4 100644 --- a/llvm/test/CodeGen/X86/pr27681.mir +++ b/llvm/test/CodeGen/X86/pr27681.mir @@ -11,7 +11,6 @@ --- # CHECK-LABEL: main name: main -allVRegsAllocated: true tracksRegLiveness: true frameInfo: stackSize: 52 diff --git a/llvm/test/DebugInfo/MIR/X86/live-debug-values-3preds.mir b/llvm/test/DebugInfo/MIR/X86/live-debug-values-3preds.mir index ea898ec1c0c..ceaec8d8568 100644 --- a/llvm/test/DebugInfo/MIR/X86/live-debug-values-3preds.mir +++ b/llvm/test/DebugInfo/MIR/X86/live-debug-values-3preds.mir @@ -157,7 +157,6 @@ name: add alignment: 4 exposesReturnsTwice: false -allVRegsAllocated: true tracksRegLiveness: true liveins: - { reg: '%edi' } diff --git a/llvm/test/DebugInfo/MIR/X86/live-debug-values.mir b/llvm/test/DebugInfo/MIR/X86/live-debug-values.mir index 920d6538ab9..31d39dce3ab 100644 --- a/llvm/test/DebugInfo/MIR/X86/live-debug-values.mir +++ b/llvm/test/DebugInfo/MIR/X86/live-debug-values.mir @@ -159,7 +159,6 @@ name: main alignment: 4 exposesReturnsTwice: false -allVRegsAllocated: true tracksRegLiveness: true liveins: - { reg: '%edi' } |
