diff options
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/DebugInfo/PowerPC/tls-fission.ll | 2 | ||||
| -rw-r--r-- | llvm/test/DebugInfo/PowerPC/tls.ll | 2 | ||||
| -rw-r--r-- | llvm/test/MC/PowerPC/ppc64-fixups.s | 32 |
3 files changed, 18 insertions, 18 deletions
diff --git a/llvm/test/DebugInfo/PowerPC/tls-fission.ll b/llvm/test/DebugInfo/PowerPC/tls-fission.ll index e8c6a13f754..5536a644d53 100644 --- a/llvm/test/DebugInfo/PowerPC/tls-fission.ll +++ b/llvm/test/DebugInfo/PowerPC/tls-fission.ll @@ -15,7 +15,7 @@ ; check that the expected TLS address description is the first thing in the debug_addr section ; CHECK: debug_addr ; CHECK-NEXT: .Laddr_sec: -; CHECK-NEXT: .quad tls@dtprel+32768 +; CHECK-NEXT: .quad tls@DTPREL+32768 @tls = thread_local global i32 0, align 4 diff --git a/llvm/test/DebugInfo/PowerPC/tls.ll b/llvm/test/DebugInfo/PowerPC/tls.ll index 7e6597c743b..85d682201be 100644 --- a/llvm/test/DebugInfo/PowerPC/tls.ll +++ b/llvm/test/DebugInfo/PowerPC/tls.ll @@ -8,7 +8,7 @@ ; DW_OP_const8u ; CHECK: .byte 14 ; The debug relocation of the address of the tls variable -; CHECK: .quad tls@dtprel+32768 +; CHECK: .quad tls@DTPREL+32768 ; DW_OP_GNU_push_tls_address ; CHECK: .byte 224 diff --git a/llvm/test/MC/PowerPC/ppc64-fixups.s b/llvm/test/MC/PowerPC/ppc64-fixups.s index 20a70c27054..0b8375bf72f 100644 --- a/llvm/test/MC/PowerPC/ppc64-fixups.s +++ b/llvm/test/MC/PowerPC/ppc64-fixups.s @@ -338,10 +338,10 @@ base: # CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_TPREL16_LO target 0x0 addi 3, 3, target@tprel@l -# CHECK-BE: addi 3, 3, target@tprel # encoding: [0x38,0x63,A,A] -# CHECK-LE: addi 3, 3, target@tprel # encoding: [A,A,0x63,0x38] -# CHECK-BE-NEXT: # fixup A - offset: 2, value: target@tprel, kind: fixup_ppc_half16 -# CHECK-LE-NEXT: # fixup A - offset: 0, value: target@tprel, kind: fixup_ppc_half16 +# CHECK-BE: addi 3, 3, target@TPREL # encoding: [0x38,0x63,A,A] +# CHECK-LE: addi 3, 3, target@TPREL # encoding: [A,A,0x63,0x38] +# CHECK-BE-NEXT: # fixup A - offset: 2, value: target@TPREL, kind: fixup_ppc_half16 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target@TPREL, kind: fixup_ppc_half16 # CHECK-BE-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TPREL16 target 0x0 # CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_TPREL16 target 0x0 addi 3, 3, target@tprel @@ -394,10 +394,10 @@ base: # CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_TPREL16_LO_DS target 0x0 ld 1, target@tprel@l(3) -# CHECK-BE: ld 1, target@tprel(3) # encoding: [0xe8,0x23,A,0bAAAAAA00] -# CHECK-LE: ld 1, target@tprel(3) # encoding: [0bAAAAAA00,A,0x23,0xe8] -# CHECK-BE-NEXT: # fixup A - offset: 2, value: target@tprel, kind: fixup_ppc_half16ds -# CHECK-LE-NEXT: # fixup A - offset: 0, value: target@tprel, kind: fixup_ppc_half16ds +# CHECK-BE: ld 1, target@TPREL(3) # encoding: [0xe8,0x23,A,0bAAAAAA00] +# CHECK-LE: ld 1, target@TPREL(3) # encoding: [0bAAAAAA00,A,0x23,0xe8] +# CHECK-BE-NEXT: # fixup A - offset: 2, value: target@TPREL, kind: fixup_ppc_half16ds +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target@TPREL, kind: fixup_ppc_half16ds # CHECK-BE-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TPREL16_DS target 0x0 # CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_TPREL16_DS target 0x0 ld 1, target@tprel(3) @@ -418,10 +418,10 @@ base: # CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_DTPREL16_LO target 0x0 addi 3, 3, target@dtprel@l -# CHECK-BE: addi 3, 3, target@dtprel # encoding: [0x38,0x63,A,A] -# CHECK-LE: addi 3, 3, target@dtprel # encoding: [A,A,0x63,0x38] -# CHECK-BE-NEXT: # fixup A - offset: 2, value: target@dtprel, kind: fixup_ppc_half16 -# CHECK-LE-NEXT: # fixup A - offset: 0, value: target@dtprel, kind: fixup_ppc_half16 +# CHECK-BE: addi 3, 3, target@DTPREL # encoding: [0x38,0x63,A,A] +# CHECK-LE: addi 3, 3, target@DTPREL # encoding: [A,A,0x63,0x38] +# CHECK-BE-NEXT: # fixup A - offset: 2, value: target@DTPREL, kind: fixup_ppc_half16 +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target@DTPREL, kind: fixup_ppc_half16 # CHECK-BE-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_DTPREL16 target 0x0 # CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_DTPREL16 target 0x0 addi 3, 3, target@dtprel @@ -474,10 +474,10 @@ base: # CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_DTPREL16_LO_DS target 0x0 ld 1, target@dtprel@l(3) -# CHECK-BE: ld 1, target@dtprel(3) # encoding: [0xe8,0x23,A,0bAAAAAA00] -# CHECK-LE: ld 1, target@dtprel(3) # encoding: [0bAAAAAA00,A,0x23,0xe8] -# CHECK-BE-NEXT: # fixup A - offset: 2, value: target@dtprel, kind: fixup_ppc_half16ds -# CHECK-LE-NEXT: # fixup A - offset: 0, value: target@dtprel, kind: fixup_ppc_half16ds +# CHECK-BE: ld 1, target@DTPREL(3) # encoding: [0xe8,0x23,A,0bAAAAAA00] +# CHECK-LE: ld 1, target@DTPREL(3) # encoding: [0bAAAAAA00,A,0x23,0xe8] +# CHECK-BE-NEXT: # fixup A - offset: 2, value: target@DTPREL, kind: fixup_ppc_half16ds +# CHECK-LE-NEXT: # fixup A - offset: 0, value: target@DTPREL, kind: fixup_ppc_half16ds # CHECK-BE-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_DTPREL16_DS target 0x0 # CHECK-LE-REL: 0x{{[0-9A-F]*[048C]}} R_PPC64_DTPREL16_DS target 0x0 ld 1, target@dtprel(3) |
