diff options
Diffstat (limited to 'llvm/test/tools')
10 files changed, 96 insertions, 20 deletions
diff --git a/llvm/test/tools/llvm-mca/X86/BtVer2/register-files-1.s b/llvm/test/tools/llvm-mca/X86/BtVer2/register-files-1.s index 0f95d5ceab9..0319bd622e2 100644 --- a/llvm/test/tools/llvm-mca/X86/BtVer2/register-files-1.s +++ b/llvm/test/tools/llvm-mca/X86/BtVer2/register-files-1.s @@ -22,7 +22,7 @@ vmulps %xmm0, %xmm0, %xmm0 # CHECK-NEXT: SQ - Store queue full: 0 # CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0 -# CHECK: Dispatch Logic - number of cycles where we saw N instructions dispatched: +# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched: # CHECK-NEXT: [# dispatched], [# cycles] # CHECK-NEXT: 0, 23 (82.1%) # CHECK-NEXT: 2, 5 (17.9%) diff --git a/llvm/test/tools/llvm-mca/X86/BtVer2/register-files-2.s b/llvm/test/tools/llvm-mca/X86/BtVer2/register-files-2.s index b68ed9ce62b..5f3fe1e6ccb 100644 --- a/llvm/test/tools/llvm-mca/X86/BtVer2/register-files-2.s +++ b/llvm/test/tools/llvm-mca/X86/BtVer2/register-files-2.s @@ -15,14 +15,14 @@ vmulps %xmm0, %xmm0, %xmm0 # CHECK-NEXT: Block RThroughput: 1.0 # CHECK: Dynamic Dispatch Stall Cycles: -# CHECK-NEXT: RAT - Register unavailable: 13 +# CHECK-NEXT: RAT - Register unavailable: 13 (46.4%) # CHECK-NEXT: RCU - Retire tokens unavailable: 0 # CHECK-NEXT: SCHEDQ - Scheduler full: 0 # CHECK-NEXT: LQ - Load queue full: 0 # CHECK-NEXT: SQ - Store queue full: 0 # CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0 -# CHECK: Dispatch Logic - number of cycles where we saw N instructions dispatched: +# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched: # CHECK-NEXT: [# dispatched], [# cycles] # CHECK-NEXT: 0, 20 (71.4%) # CHECK-NEXT: 1, 6 (21.4%) diff --git a/llvm/test/tools/llvm-mca/X86/BtVer2/register-files-3.s b/llvm/test/tools/llvm-mca/X86/BtVer2/register-files-3.s index 12aeed7acb2..342f122d66b 100644 --- a/llvm/test/tools/llvm-mca/X86/BtVer2/register-files-3.s +++ b/llvm/test/tools/llvm-mca/X86/BtVer2/register-files-3.s @@ -25,17 +25,17 @@ idiv %eax # CHECK-NEXT: 2 25 25.00 U idivl %eax # CHECK: Dynamic Dispatch Stall Cycles: -# CHECK-NEXT: RAT - Register unavailable: 26 +# CHECK-NEXT: RAT - Register unavailable: 26 (47.3%) # CHECK-NEXT: RCU - Retire tokens unavailable: 0 # CHECK-NEXT: SCHEDQ - Scheduler full: 0 # CHECK-NEXT: LQ - Load queue full: 0 # CHECK-NEXT: SQ - Store queue full: 0 # CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0 -# CHECK: Dispatch Logic - number of cycles where we saw N instructions dispatched: +# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched: # CHECK-NEXT: [# dispatched], [# cycles] # CHECK-NEXT: 0, 53 (96.4%) -# CHECK-NEXT: 1, 2 (3.6%) +# CHECK-NEXT: 2, 2 (3.6%) # CHECK: Register File statistics: # CHECK-NEXT: Total number of mappings created: 6 diff --git a/llvm/test/tools/llvm-mca/X86/BtVer2/register-files-4.s b/llvm/test/tools/llvm-mca/X86/BtVer2/register-files-4.s index d67d5e456c3..0291ef2ea2b 100644 --- a/llvm/test/tools/llvm-mca/X86/BtVer2/register-files-4.s +++ b/llvm/test/tools/llvm-mca/X86/BtVer2/register-files-4.s @@ -25,17 +25,17 @@ idiv %eax # CHECK-NEXT: 2 25 25.00 U idivl %eax # CHECK: Dynamic Dispatch Stall Cycles: -# CHECK-NEXT: RAT - Register unavailable: 6 +# CHECK-NEXT: RAT - Register unavailable: 6 (1.1%) # CHECK-NEXT: RCU - Retire tokens unavailable: 0 # CHECK-NEXT: SCHEDQ - Scheduler full: 0 # CHECK-NEXT: LQ - Load queue full: 0 # CHECK-NEXT: SQ - Store queue full: 0 # CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0 -# CHECK: Dispatch Logic - number of cycles where we saw N instructions dispatched: +# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched: # CHECK-NEXT: [# dispatched], [# cycles] # CHECK-NEXT: 0, 531 (96.0%) -# CHECK-NEXT: 1, 22 (4.0%) +# CHECK-NEXT: 2, 22 (4.0%) # CHECK: Register File statistics: # CHECK-NEXT: Total number of mappings created: 66 diff --git a/llvm/test/tools/llvm-mca/X86/BtVer2/register-files-5.s b/llvm/test/tools/llvm-mca/X86/BtVer2/register-files-5.s index 3d09bc788bd..f676e77bf1e 100644 --- a/llvm/test/tools/llvm-mca/X86/BtVer2/register-files-5.s +++ b/llvm/test/tools/llvm-mca/X86/BtVer2/register-files-5.s @@ -47,16 +47,16 @@ # CHECK: Dynamic Dispatch Stall Cycles: # CHECK-NEXT: RAT - Register unavailable: 0 -# CHECK-NEXT: RCU - Retire tokens unavailable: 8 +# CHECK-NEXT: RCU - Retire tokens unavailable: 8 (11.6%) # CHECK-NEXT: SCHEDQ - Scheduler full: 0 # CHECK-NEXT: LQ - Load queue full: 0 # CHECK-NEXT: SQ - Store queue full: 0 # CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0 -# CHECK: Dispatch Logic - number of cycles where we saw N instructions dispatched: +# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched: # CHECK-NEXT: [# dispatched], [# cycles] # CHECK-NEXT: 0, 36 (52.2%) -# CHECK-NEXT: 1, 33 (47.8%) +# CHECK-NEXT: 2, 33 (47.8%) # CHECK: Register File statistics: # CHECK-NEXT: Total number of mappings created: 66 diff --git a/llvm/test/tools/llvm-mca/X86/Haswell/cmpxchg16b.s b/llvm/test/tools/llvm-mca/X86/Haswell/cmpxchg16b.s new file mode 100644 index 00000000000..f0a0567a682 --- /dev/null +++ b/llvm/test/tools/llvm-mca/X86/Haswell/cmpxchg16b.s @@ -0,0 +1,76 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=haswell -timeline -timeline-max-iterations=3 -dispatch-stats < %s | FileCheck %s + +cmpxchg16b (%rsi) + +# CHECK: Iterations: 100 +# CHECK-NEXT: Instructions: 100 +# CHECK-NEXT: Total Cycles: 2203 +# CHECK-NEXT: Total uOps: 1900 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 0.86 +# CHECK-NEXT: IPC: 0.05 +# CHECK-NEXT: Block RThroughput: 4.8 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 19 22 4.00 * * cmpxchg16b (%rsi) + +# CHECK: Dynamic Dispatch Stall Cycles: +# CHECK-NEXT: RAT - Register unavailable: 0 +# CHECK-NEXT: RCU - Retire tokens unavailable: 1487 (67.5%) +# CHECK-NEXT: SCHEDQ - Scheduler full: 0 +# CHECK-NEXT: LQ - Load queue full: 0 +# CHECK-NEXT: SQ - Store queue full: 0 +# CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0 + +# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched: +# CHECK-NEXT: [# dispatched], [# cycles] +# CHECK-NEXT: 0, 1703 (77.3%) +# CHECK-NEXT: 3, 100 (4.5%) +# CHECK-NEXT: 4, 400 (18.2%) + +# CHECK: Resources: +# CHECK-NEXT: [0] - HWDivider +# CHECK-NEXT: [1] - HWFPDivider +# CHECK-NEXT: [2] - HWPort0 +# CHECK-NEXT: [3] - HWPort1 +# CHECK-NEXT: [4] - HWPort2 +# CHECK-NEXT: [5] - HWPort3 +# CHECK-NEXT: [6] - HWPort4 +# CHECK-NEXT: [7] - HWPort5 +# CHECK-NEXT: [8] - HWPort6 +# CHECK-NEXT: [9] - HWPort7 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] +# CHECK-NEXT: - - 2.00 6.00 0.66 0.67 1.00 4.00 4.00 0.67 + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions: +# CHECK-NEXT: - - 2.00 6.00 0.66 0.67 1.00 4.00 4.00 0.67 cmpxchg16b (%rsi) + +# CHECK: Timeline view: +# CHECK-NEXT: 0123456789 0123456789 0123456789 +# CHECK-NEXT: Index 0123456789 0123456789 0123456789 012345678 + +# CHECK: [0,0] DeeeeeeeeeeeeeeeeeeeeeeER. . . . . . . . . . cmpxchg16b (%rsi) +# CHECK-NEXT: [1,0] . D=================eeeeeeeeeeeeeeeeeeeeeeER . . . . . cmpxchg16b (%rsi) +# CHECK-NEXT: [2,0] . . D==================================eeeeeeeeeeeeeeeeeeeeeeER cmpxchg16b (%rsi) + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 3 18.0 0.3 0.0 cmpxchg16b (%rsi) diff --git a/llvm/test/tools/llvm-mca/X86/option-all-stats-1.s b/llvm/test/tools/llvm-mca/X86/option-all-stats-1.s index 5763caaf985..60276c3ee07 100644 --- a/llvm/test/tools/llvm-mca/X86/option-all-stats-1.s +++ b/llvm/test/tools/llvm-mca/X86/option-all-stats-1.s @@ -30,12 +30,12 @@ add %eax, %eax # FULLREPORT: Dynamic Dispatch Stall Cycles: # FULLREPORT-NEXT: RAT - Register unavailable: 0 # FULLREPORT-NEXT: RCU - Retire tokens unavailable: 0 -# FULLREPORT-NEXT: SCHEDQ - Scheduler full: 61 +# FULLREPORT-NEXT: SCHEDQ - Scheduler full: 61 (59.2%) # FULLREPORT-NEXT: LQ - Load queue full: 0 # FULLREPORT-NEXT: SQ - Store queue full: 0 # FULLREPORT-NEXT: GROUP - Static restrictions on the dispatch group: 0 -# FULLREPORT: Dispatch Logic - number of cycles where we saw N instructions dispatched: +# FULLREPORT: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched: # FULLREPORT-NEXT: [# dispatched], [# cycles] # FULLREPORT-NEXT: 0, 22 (21.4%) # FULLREPORT-NEXT: 1, 62 (60.2%) diff --git a/llvm/test/tools/llvm-mca/X86/option-all-stats-2.s b/llvm/test/tools/llvm-mca/X86/option-all-stats-2.s index 3e8c8bece2a..f5cfdc314c6 100644 --- a/llvm/test/tools/llvm-mca/X86/option-all-stats-2.s +++ b/llvm/test/tools/llvm-mca/X86/option-all-stats-2.s @@ -31,12 +31,12 @@ add %eax, %eax # FULL: Dynamic Dispatch Stall Cycles: # FULL-NEXT: RAT - Register unavailable: 0 # FULL-NEXT: RCU - Retire tokens unavailable: 0 -# FULL-NEXT: SCHEDQ - Scheduler full: 61 +# FULL-NEXT: SCHEDQ - Scheduler full: 61 (59.2%) # FULL-NEXT: LQ - Load queue full: 0 # FULL-NEXT: SQ - Store queue full: 0 # FULL-NEXT: GROUP - Static restrictions on the dispatch group: 0 -# FULL: Dispatch Logic - number of cycles where we saw N instructions dispatched: +# FULL: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched: # FULL-NEXT: [# dispatched], [# cycles] # FULL-NEXT: 0, 22 (21.4%) # FULL-NEXT: 1, 62 (60.2%) diff --git a/llvm/test/tools/llvm-mca/X86/option-all-views-1.s b/llvm/test/tools/llvm-mca/X86/option-all-views-1.s index 8950014f6b9..e707a66f0cb 100644 --- a/llvm/test/tools/llvm-mca/X86/option-all-views-1.s +++ b/llvm/test/tools/llvm-mca/X86/option-all-views-1.s @@ -32,12 +32,12 @@ add %eax, %eax # FULLREPORT: Dynamic Dispatch Stall Cycles: # FULLREPORT-NEXT: RAT - Register unavailable: 0 # FULLREPORT-NEXT: RCU - Retire tokens unavailable: 0 -# FULLREPORT-NEXT: SCHEDQ - Scheduler full: 61 +# FULLREPORT-NEXT: SCHEDQ - Scheduler full: 61 (59.2%) # FULLREPORT-NEXT: LQ - Load queue full: 0 # FULLREPORT-NEXT: SQ - Store queue full: 0 # FULLREPORT-NEXT: GROUP - Static restrictions on the dispatch group: 0 -# FULLREPORT: Dispatch Logic - number of cycles where we saw N instructions dispatched: +# FULLREPORT: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched: # FULLREPORT-NEXT: [# dispatched], [# cycles] # FULLREPORT-NEXT: 0, 22 (21.4%) # FULLREPORT-NEXT: 1, 62 (60.2%) diff --git a/llvm/test/tools/llvm-mca/X86/option-all-views-2.s b/llvm/test/tools/llvm-mca/X86/option-all-views-2.s index 30c194777e1..b71ec2a7172 100644 --- a/llvm/test/tools/llvm-mca/X86/option-all-views-2.s +++ b/llvm/test/tools/llvm-mca/X86/option-all-views-2.s @@ -31,12 +31,12 @@ add %eax, %eax # ALL: Dynamic Dispatch Stall Cycles: # ALL-NEXT: RAT - Register unavailable: 0 # ALL-NEXT: RCU - Retire tokens unavailable: 0 -# ALL-NEXT: SCHEDQ - Scheduler full: 61 +# ALL-NEXT: SCHEDQ - Scheduler full: 61 (59.2%) # ALL-NEXT: LQ - Load queue full: 0 # ALL-NEXT: SQ - Store queue full: 0 # ALL-NEXT: GROUP - Static restrictions on the dispatch group: 0 -# ALL: Dispatch Logic - number of cycles where we saw N instructions dispatched: +# ALL: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched: # ALL-NEXT: [# dispatched], [# cycles] # ALL-NEXT: 0, 22 (21.4%) # ALL-NEXT: 1, 62 (60.2%) |
