diff options
Diffstat (limited to 'llvm/test/Transforms/PhaseOrdering/PowerPC')
4 files changed, 305 insertions, 0 deletions
diff --git a/llvm/test/Transforms/PhaseOrdering/PowerPC/lit.local.cfg b/llvm/test/Transforms/PhaseOrdering/PowerPC/lit.local.cfg new file mode 100644 index 00000000000..091332439b1 --- /dev/null +++ b/llvm/test/Transforms/PhaseOrdering/PowerPC/lit.local.cfg @@ -0,0 +1,2 @@ +if not 'PowerPC' in config.root.targets: + config.unsupported = True diff --git a/llvm/test/Transforms/PhaseOrdering/PowerPC/memCmpUsedInZeroEqualityComparison.ll b/llvm/test/Transforms/PhaseOrdering/PowerPC/memCmpUsedInZeroEqualityComparison.ll new file mode 100644 index 00000000000..c32f6b2a16a --- /dev/null +++ b/llvm/test/Transforms/PhaseOrdering/PowerPC/memCmpUsedInZeroEqualityComparison.ll @@ -0,0 +1,174 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; RUN: opt < %s -O2 -S -mcpu=pwr8 < %s | FileCheck %s +target datalayout = "e-m:e-i64:64-n32:64" +target triple = "powerpc64le-unknown-linux-gnu" + +@zeroEqualityTest01.buffer1 = private unnamed_addr constant [3 x i32] [i32 1, i32 2, i32 4], align 4 +@zeroEqualityTest01.buffer2 = private unnamed_addr constant [3 x i32] [i32 1, i32 2, i32 3], align 4 +@zeroEqualityTest02.buffer1 = private unnamed_addr constant [4 x i32] [i32 4, i32 0, i32 0, i32 0], align 4 +@zeroEqualityTest02.buffer2 = private unnamed_addr constant [4 x i32] [i32 3, i32 0, i32 0, i32 0], align 4 +@zeroEqualityTest03.buffer1 = private unnamed_addr constant [4 x i32] [i32 0, i32 0, i32 0, i32 3], align 4 +@zeroEqualityTest03.buffer2 = private unnamed_addr constant [4 x i32] [i32 0, i32 0, i32 0, i32 4], align 4 +@zeroEqualityTest04.buffer1 = private unnamed_addr constant [15 x i32] [i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14], align 4 +@zeroEqualityTest04.buffer2 = private unnamed_addr constant [15 x i32] [i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 13], align 4 + +declare signext i32 @memcmp(i8* nocapture, i8* nocapture, i64) local_unnamed_addr #1 + +; Check 4 bytes - requires 1 load for each param. +define signext i32 @zeroEqualityTest02(i8* %x, i8* %y) { +; CHECK-LABEL: @zeroEqualityTest02( +; CHECK-NEXT: [[TMP1:%.*]] = bitcast i8* [[X:%.*]] to i32* +; CHECK-NEXT: [[TMP2:%.*]] = bitcast i8* [[Y:%.*]] to i32* +; CHECK-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP1]], align 4 +; CHECK-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP2]], align 4 +; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i32 [[TMP3]], [[TMP4]] +; CHECK-NEXT: [[TMP6:%.*]] = zext i1 [[TMP5]] to i32 +; CHECK-NEXT: ret i32 [[TMP6]] +; + %call = tail call signext i32 @memcmp(i8* %x, i8* %y, i64 4) + %not.cmp = icmp ne i32 %call, 0 + %. = zext i1 %not.cmp to i32 + ret i32 %. +} + +; Check 16 bytes - requires 2 loads for each param (or use vectors?). +define signext i32 @zeroEqualityTest01(i8* %x, i8* %y) { +; CHECK-LABEL: @zeroEqualityTest01( +; CHECK-NEXT: loadbb: +; CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[X:%.*]] to i64* +; CHECK-NEXT: [[TMP1:%.*]] = bitcast i8* [[Y:%.*]] to i64* +; CHECK-NEXT: [[TMP2:%.*]] = load i64, i64* [[TMP0]], align 8 +; CHECK-NEXT: [[TMP3:%.*]] = load i64, i64* [[TMP1]], align 8 +; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i64 [[TMP2]], [[TMP3]] +; CHECK-NEXT: br i1 [[TMP4]], label [[LOADBB1:%.*]], label [[RES_BLOCK:%.*]] +; CHECK: res_block: +; CHECK-NEXT: br label [[ENDBLOCK:%.*]] +; CHECK: loadbb1: +; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i8, i8* [[X]], i64 8 +; CHECK-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to i64* +; CHECK-NEXT: [[TMP7:%.*]] = getelementptr i8, i8* [[Y]], i64 8 +; CHECK-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i64* +; CHECK-NEXT: [[TMP9:%.*]] = load i64, i64* [[TMP6]], align 8 +; CHECK-NEXT: [[TMP10:%.*]] = load i64, i64* [[TMP8]], align 8 +; CHECK-NEXT: [[TMP11:%.*]] = icmp eq i64 [[TMP9]], [[TMP10]] +; CHECK-NEXT: br i1 [[TMP11]], label [[ENDBLOCK]], label [[RES_BLOCK]] +; CHECK: endblock: +; CHECK-NEXT: [[PHI_RES:%.*]] = phi i32 [ 0, [[LOADBB1]] ], [ 1, [[RES_BLOCK]] ] +; CHECK-NEXT: ret i32 [[PHI_RES]] +; + %call = tail call signext i32 @memcmp(i8* %x, i8* %y, i64 16) + %not.tobool = icmp ne i32 %call, 0 + %. = zext i1 %not.tobool to i32 + ret i32 %. +} + +; Check 7 bytes - requires 3 loads for each param. +define signext i32 @zeroEqualityTest03(i8* %x, i8* %y) { +; CHECK-LABEL: @zeroEqualityTest03( +; CHECK-NEXT: loadbb: +; CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[X:%.*]] to i32* +; CHECK-NEXT: [[TMP1:%.*]] = bitcast i8* [[Y:%.*]] to i32* +; CHECK-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP0]], align 4 +; CHECK-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP1]], align 4 +; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP2]], [[TMP3]] +; CHECK-NEXT: br i1 [[TMP4]], label [[LOADBB1:%.*]], label [[RES_BLOCK:%.*]] +; CHECK: res_block: +; CHECK-NEXT: br label [[ENDBLOCK:%.*]] +; CHECK: loadbb1: +; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i8, i8* [[X]], i64 4 +; CHECK-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to i16* +; CHECK-NEXT: [[TMP7:%.*]] = getelementptr i8, i8* [[Y]], i64 4 +; CHECK-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i16* +; CHECK-NEXT: [[TMP9:%.*]] = load i16, i16* [[TMP6]], align 2 +; CHECK-NEXT: [[TMP10:%.*]] = load i16, i16* [[TMP8]], align 2 +; CHECK-NEXT: [[TMP11:%.*]] = icmp eq i16 [[TMP9]], [[TMP10]] +; CHECK-NEXT: br i1 [[TMP11]], label [[LOADBB2:%.*]], label [[RES_BLOCK]] +; CHECK: loadbb2: +; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i8, i8* [[X]], i64 6 +; CHECK-NEXT: [[TMP13:%.*]] = getelementptr i8, i8* [[Y]], i64 6 +; CHECK-NEXT: [[TMP14:%.*]] = load i8, i8* [[TMP12]], align 1 +; CHECK-NEXT: [[TMP15:%.*]] = load i8, i8* [[TMP13]], align 1 +; CHECK-NEXT: [[TMP16:%.*]] = icmp eq i8 [[TMP14]], [[TMP15]] +; CHECK-NEXT: br i1 [[TMP16]], label [[ENDBLOCK]], label [[RES_BLOCK]] +; CHECK: endblock: +; CHECK-NEXT: [[PHI_RES:%.*]] = phi i32 [ 0, [[LOADBB2]] ], [ 1, [[RES_BLOCK]] ] +; CHECK-NEXT: ret i32 [[PHI_RES]] +; + %call = tail call signext i32 @memcmp(i8* %x, i8* %y, i64 7) + %not.lnot = icmp ne i32 %call, 0 + %cond = zext i1 %not.lnot to i32 + ret i32 %cond +} + +; Validate with > 0 +define signext i32 @zeroEqualityTest04() { +; CHECK-LABEL: @zeroEqualityTest04( +; CHECK-NEXT: loadbb: +; CHECK-NEXT: ret i32 0 +; + %call = tail call signext i32 @memcmp(i8* bitcast ([4 x i32]* @zeroEqualityTest02.buffer1 to i8*), i8* bitcast ([4 x i32]* @zeroEqualityTest02.buffer2 to i8*), i64 16) + %not.cmp = icmp slt i32 %call, 1 + %. = zext i1 %not.cmp to i32 + ret i32 %. +} + +; Validate with < 0 +define signext i32 @zeroEqualityTest05() { +; CHECK-LABEL: @zeroEqualityTest05( +; CHECK-NEXT: loadbb: +; CHECK-NEXT: ret i32 0 +; + %call = tail call signext i32 @memcmp(i8* bitcast ([4 x i32]* @zeroEqualityTest03.buffer1 to i8*), i8* bitcast ([4 x i32]* @zeroEqualityTest03.buffer2 to i8*), i64 16) + %call.lobit = lshr i32 %call, 31 + %call.lobit.not = xor i32 %call.lobit, 1 + ret i32 %call.lobit.not +} + +; Validate with memcmp()?: +define signext i32 @equalityFoldTwoConstants() { +; CHECK-LABEL: @equalityFoldTwoConstants( +; CHECK-NEXT: loadbb: +; CHECK-NEXT: ret i32 1 +; + %call = tail call signext i32 @memcmp(i8* bitcast ([15 x i32]* @zeroEqualityTest04.buffer1 to i8*), i8* bitcast ([15 x i32]* @zeroEqualityTest04.buffer2 to i8*), i64 16) + %not.tobool = icmp eq i32 %call, 0 + %cond = zext i1 %not.tobool to i32 + ret i32 %cond +} + +define signext i32 @equalityFoldOneConstant(i8* %X) { +; CHECK-LABEL: @equalityFoldOneConstant( +; CHECK-NEXT: loadbb: +; CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[X:%.*]] to i64* +; CHECK-NEXT: [[TMP1:%.*]] = load i64, i64* [[TMP0]], align 8 +; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 4294967296 +; CHECK-NEXT: br i1 [[TMP2]], label [[LOADBB1:%.*]], label [[RES_BLOCK:%.*]] +; CHECK: res_block: +; CHECK-NEXT: br label [[ENDBLOCK:%.*]] +; CHECK: loadbb1: +; CHECK-NEXT: [[TMP3:%.*]] = getelementptr i8, i8* [[X]], i64 8 +; CHECK-NEXT: [[TMP4:%.*]] = bitcast i8* [[TMP3]] to i64* +; CHECK-NEXT: [[TMP5:%.*]] = load i64, i64* [[TMP4]], align 8 +; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 12884901890 +; CHECK-NEXT: br i1 [[TMP6]], label [[ENDBLOCK]], label [[RES_BLOCK]] +; CHECK: endblock: +; CHECK-NEXT: [[PHI_RES:%.*]] = phi i32 [ 1, [[LOADBB1]] ], [ 0, [[RES_BLOCK]] ] +; CHECK-NEXT: ret i32 [[PHI_RES]] +; + %call = tail call signext i32 @memcmp(i8* bitcast ([15 x i32]* @zeroEqualityTest04.buffer1 to i8*), i8* %X, i64 16) + %not.tobool = icmp eq i32 %call, 0 + %cond = zext i1 %not.tobool to i32 + ret i32 %cond +} + +define i1 @length2_eq_nobuiltin_attr(i8* %X, i8* %Y) { +; CHECK-LABEL: @length2_eq_nobuiltin_attr( +; CHECK-NEXT: [[M:%.*]] = tail call signext i32 @memcmp(i8* [[X:%.*]], i8* [[Y:%.*]], i64 2) #2 +; CHECK-NEXT: [[C:%.*]] = icmp eq i32 [[M]], 0 +; CHECK-NEXT: ret i1 [[C]] +; + %m = tail call signext i32 @memcmp(i8* %X, i8* %Y, i64 2) nobuiltin + %c = icmp eq i32 %m, 0 + ret i1 %c +} + diff --git a/llvm/test/Transforms/PhaseOrdering/PowerPC/memcmp-mergeexpand.ll b/llvm/test/Transforms/PhaseOrdering/PowerPC/memcmp-mergeexpand.ll new file mode 100644 index 00000000000..cab9ad0fefb --- /dev/null +++ b/llvm/test/Transforms/PhaseOrdering/PowerPC/memcmp-mergeexpand.ll @@ -0,0 +1,49 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; RUN: opt -S -mergeicmps -expandmemcmp -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux < %s | FileCheck %s --check-prefix=PPC64LE + +; This tests interaction between MergeICmp and ExpandMemCmp. + +%"struct.std::pair" = type { i32, i32 } + +define zeroext i1 @opeq1( +; PPC64LE-LABEL: @opeq1( +; PPC64LE-NEXT: "entry+land.rhs.i": +; PPC64LE-NEXT: [[TMP0:%.*]] = getelementptr inbounds %"struct.std::pair", %"struct.std::pair"* [[A:%.*]], i64 0, i32 0 +; PPC64LE-NEXT: [[TMP1:%.*]] = getelementptr inbounds %"struct.std::pair", %"struct.std::pair"* [[B:%.*]], i64 0, i32 0 +; PPC64LE-NEXT: [[CSTR:%.*]] = bitcast i32* [[TMP0]] to i8* +; PPC64LE-NEXT: [[CSTR1:%.*]] = bitcast i32* [[TMP1]] to i8* +; PPC64LE-NEXT: [[TMP2:%.*]] = bitcast i8* [[CSTR]] to i64* +; PPC64LE-NEXT: [[TMP3:%.*]] = bitcast i8* [[CSTR1]] to i64* +; PPC64LE-NEXT: [[TMP4:%.*]] = load i64, i64* [[TMP2]] +; PPC64LE-NEXT: [[TMP5:%.*]] = load i64, i64* [[TMP3]] +; PPC64LE-NEXT: [[TMP6:%.*]] = icmp ne i64 [[TMP4]], [[TMP5]] +; PPC64LE-NEXT: [[TMP7:%.*]] = zext i1 [[TMP6]] to i32 +; PPC64LE-NEXT: [[TMP8:%.*]] = icmp eq i32 [[TMP7]], 0 +; PPC64LE-NEXT: br label [[OPEQ1_EXIT:%.*]] +; PPC64LE: opeq1.exit: +; PPC64LE-NEXT: ret i1 [[TMP8]] +; + %"struct.std::pair"* nocapture readonly dereferenceable(8) %a, + %"struct.std::pair"* nocapture readonly dereferenceable(8) %b) local_unnamed_addr #0 { +entry: + %first.i = getelementptr inbounds %"struct.std::pair", %"struct.std::pair"* %a, i64 0, i32 0 + %0 = load i32, i32* %first.i, align 4 + %first1.i = getelementptr inbounds %"struct.std::pair", %"struct.std::pair"* %b, i64 0, i32 0 + %1 = load i32, i32* %first1.i, align 4 + %cmp.i = icmp eq i32 %0, %1 + br i1 %cmp.i, label %land.rhs.i, label %opeq1.exit + +land.rhs.i: + %second.i = getelementptr inbounds %"struct.std::pair", %"struct.std::pair"* %a, i64 0, i32 1 + %2 = load i32, i32* %second.i, align 4 + %second2.i = getelementptr inbounds %"struct.std::pair", %"struct.std::pair"* %b, i64 0, i32 1 + %3 = load i32, i32* %second2.i, align 4 + %cmp3.i = icmp eq i32 %2, %3 + br label %opeq1.exit + +opeq1.exit: + %4 = phi i1 [ false, %entry ], [ %cmp3.i, %land.rhs.i ] + ret i1 %4 +} + + diff --git a/llvm/test/Transforms/PhaseOrdering/PowerPC/memcmp.ll b/llvm/test/Transforms/PhaseOrdering/PowerPC/memcmp.ll new file mode 100644 index 00000000000..e881e685555 --- /dev/null +++ b/llvm/test/Transforms/PhaseOrdering/PowerPC/memcmp.ll @@ -0,0 +1,80 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; RUN: opt < %s -O2 -S -mcpu=pwr8 -mtriple=powerpc64le-unknown-gnu-linux | FileCheck %s -check-prefix=CHECK + +define signext i32 @memcmp8(i32* nocapture readonly %buffer1, i32* nocapture readonly %buffer2) { +; CHECK-LABEL: @memcmp8( +; CHECK-NEXT: [[TMP1:%.*]] = bitcast i32* [[BUFFER1:%.*]] to i64* +; CHECK-NEXT: [[TMP2:%.*]] = bitcast i32* [[BUFFER2:%.*]] to i64* +; CHECK-NEXT: [[TMP3:%.*]] = load i64, i64* [[TMP1]], align 4 +; CHECK-NEXT: [[TMP4:%.*]] = load i64, i64* [[TMP2]], align 4 +; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.bswap.i64(i64 [[TMP3]]) +; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.bswap.i64(i64 [[TMP4]]) +; CHECK-NEXT: [[TMP7:%.*]] = icmp ugt i64 [[TMP5]], [[TMP6]] +; CHECK-NEXT: [[TMP8:%.*]] = icmp ult i64 [[TMP5]], [[TMP6]] +; CHECK-NEXT: [[TMP9:%.*]] = zext i1 [[TMP7]] to i32 +; CHECK-NEXT: [[TMP10:%.*]] = zext i1 [[TMP8]] to i32 +; CHECK-NEXT: [[TMP11:%.*]] = sub nsw i32 [[TMP9]], [[TMP10]] +; CHECK-NEXT: ret i32 [[TMP11]] +; + %t0 = bitcast i32* %buffer1 to i8* + %t1 = bitcast i32* %buffer2 to i8* + %call = tail call signext i32 @memcmp(i8* %t0, i8* %t1, i64 8) + ret i32 %call +} + +define signext i32 @memcmp4(i32* nocapture readonly %buffer1, i32* nocapture readonly %buffer2) { +; CHECK-LABEL: @memcmp4( +; CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* [[BUFFER1:%.*]], align 4 +; CHECK-NEXT: [[TMP2:%.*]] = load i32, i32* [[BUFFER2:%.*]], align 4 +; CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.bswap.i32(i32 [[TMP1]]) +; CHECK-NEXT: [[TMP4:%.*]] = call i32 @llvm.bswap.i32(i32 [[TMP2]]) +; CHECK-NEXT: [[TMP5:%.*]] = icmp ugt i32 [[TMP3]], [[TMP4]] +; CHECK-NEXT: [[TMP6:%.*]] = icmp ult i32 [[TMP3]], [[TMP4]] +; CHECK-NEXT: [[TMP7:%.*]] = zext i1 [[TMP5]] to i32 +; CHECK-NEXT: [[TMP8:%.*]] = zext i1 [[TMP6]] to i32 +; CHECK-NEXT: [[TMP9:%.*]] = sub nsw i32 [[TMP7]], [[TMP8]] +; CHECK-NEXT: ret i32 [[TMP9]] +; + %t0 = bitcast i32* %buffer1 to i8* + %t1 = bitcast i32* %buffer2 to i8* + %call = tail call signext i32 @memcmp(i8* %t0, i8* %t1, i64 4) + ret i32 %call +} + +define signext i32 @memcmp2(i32* nocapture readonly %buffer1, i32* nocapture readonly %buffer2) { +; CHECK-LABEL: @memcmp2( +; CHECK-NEXT: [[TMP1:%.*]] = bitcast i32* [[BUFFER1:%.*]] to i16* +; CHECK-NEXT: [[TMP2:%.*]] = bitcast i32* [[BUFFER2:%.*]] to i16* +; CHECK-NEXT: [[TMP3:%.*]] = load i16, i16* [[TMP1]], align 2 +; CHECK-NEXT: [[TMP4:%.*]] = load i16, i16* [[TMP2]], align 2 +; CHECK-NEXT: [[TMP5:%.*]] = call i16 @llvm.bswap.i16(i16 [[TMP3]]) +; CHECK-NEXT: [[TMP6:%.*]] = call i16 @llvm.bswap.i16(i16 [[TMP4]]) +; CHECK-NEXT: [[TMP7:%.*]] = zext i16 [[TMP5]] to i32 +; CHECK-NEXT: [[TMP8:%.*]] = zext i16 [[TMP6]] to i32 +; CHECK-NEXT: [[TMP9:%.*]] = sub nsw i32 [[TMP7]], [[TMP8]] +; CHECK-NEXT: ret i32 [[TMP9]] +; + %t0 = bitcast i32* %buffer1 to i8* + %t1 = bitcast i32* %buffer2 to i8* + %call = tail call signext i32 @memcmp(i8* %t0, i8* %t1, i64 2) + ret i32 %call +} + +define signext i32 @memcmp1(i32* nocapture readonly %buffer1, i32* nocapture readonly %buffer2) { +; CHECK-LABEL: @memcmp1( +; CHECK-NEXT: [[T0:%.*]] = bitcast i32* [[BUFFER1:%.*]] to i8* +; CHECK-NEXT: [[T1:%.*]] = bitcast i32* [[BUFFER2:%.*]] to i8* +; CHECK-NEXT: [[LHSC:%.*]] = load i8, i8* [[T0]], align 1 +; CHECK-NEXT: [[LHSV:%.*]] = zext i8 [[LHSC]] to i32 +; CHECK-NEXT: [[RHSC:%.*]] = load i8, i8* [[T1]], align 1 +; CHECK-NEXT: [[RHSV:%.*]] = zext i8 [[RHSC]] to i32 +; CHECK-NEXT: [[CHARDIFF:%.*]] = sub nsw i32 [[LHSV]], [[RHSV]] +; CHECK-NEXT: ret i32 [[CHARDIFF]] +; + %t0 = bitcast i32* %buffer1 to i8* + %t1 = bitcast i32* %buffer2 to i8* + %call = tail call signext i32 @memcmp(i8* %t0, i8* %t1, i64 1) #2 + ret i32 %call +} + +declare signext i32 @memcmp(i8*, i8*, i64) |
