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-rw-r--r--llvm/test/Transforms/InstCombine/and.ll5
-rw-r--r--llvm/test/Transforms/InstCombine/zext.ll2
2 files changed, 3 insertions, 4 deletions
diff --git a/llvm/test/Transforms/InstCombine/and.ll b/llvm/test/Transforms/InstCombine/and.ll
index 40f5cf27136..b433574974a 100644
--- a/llvm/test/Transforms/InstCombine/and.ll
+++ b/llvm/test/Transforms/InstCombine/and.ll
@@ -382,12 +382,11 @@ define i32 @test31(i1 %X) {
ret i32 %A
}
-; FIXME: Demanded bit analysis allows us to eliminate the add.
+; Demanded bit analysis allows us to eliminate the add.
define <2 x i32> @and_demanded_bits_splat_vec(<2 x i32> %x) {
; CHECK-LABEL: @and_demanded_bits_splat_vec(
-; CHECK-NEXT: [[Y:%.*]] = add <2 x i32> %x, <i32 8, i32 8>
-; CHECK-NEXT: [[Z:%.*]] = and <2 x i32> [[Y]], <i32 7, i32 7>
+; CHECK-NEXT: [[Z:%.*]] = and <2 x i32> %x, <i32 7, i32 7>
; CHECK-NEXT: ret <2 x i32> [[Z]]
;
%y = add <2 x i32> %x, <i32 8, i32 8>
diff --git a/llvm/test/Transforms/InstCombine/zext.ll b/llvm/test/Transforms/InstCombine/zext.ll
index 740509809d1..887d839cb8c 100644
--- a/llvm/test/Transforms/InstCombine/zext.ll
+++ b/llvm/test/Transforms/InstCombine/zext.ll
@@ -35,7 +35,7 @@ define <2 x i64> @test3(<2 x i64> %A) {
define <2 x i64> @test4(<2 x i64> %A) {
; CHECK-LABEL: @test4(
-; CHECK-NEXT: [[TMP1:%.*]] = xor <2 x i64> %A, <i64 4294967295, i64 4294967295>
+; CHECK-NEXT: [[TMP1:%.*]] = xor <2 x i64> %A, <i64 63, i64 63>
; CHECK-NEXT: [[XOR:%.*]] = and <2 x i64> [[TMP1]], <i64 23, i64 42>
; CHECK-NEXT: ret <2 x i64> [[XOR]]
;
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