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-rw-r--r--llvm/test/TableGen/Common/GlobalISelEmitterCommon.td4
1 files changed, 4 insertions, 0 deletions
diff --git a/llvm/test/TableGen/Common/GlobalISelEmitterCommon.td b/llvm/test/TableGen/Common/GlobalISelEmitterCommon.td
index f96e0fec760..2fe84fb9529 100644
--- a/llvm/test/TableGen/Common/GlobalISelEmitterCommon.td
+++ b/llvm/test/TableGen/Common/GlobalISelEmitterCommon.td
@@ -2,6 +2,10 @@
def MyTargetISA : InstrInfo;
def MyTarget : Target { let InstructionSet = MyTargetISA; }
+class MyTargetGenericInstruction : GenericInstruction {
+ let Namespace = "MyTarget";
+}
+
def R0 : Register<"r0"> { let Namespace = "MyTarget"; }
def GPR32 : RegisterClass<"MyTarget", [i32], 32, (add R0)>;
def GPR32Op : RegisterOperand<GPR32>;
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