diff options
Diffstat (limited to 'llvm/test/MC')
| -rw-r--r-- | llvm/test/MC/AArch64/arm64-aliases.s | 95 | ||||
| -rw-r--r-- | llvm/test/MC/AArch64/arm64-arithmetic-encoding.s | 16 | ||||
| -rw-r--r-- | llvm/test/MC/AArch64/basic-a64-instructions.s | 10 | ||||
| -rw-r--r-- | llvm/test/MC/AArch64/ldr-pseudo.s | 14 | ||||
| -rw-r--r-- | llvm/test/MC/AArch64/single-slash.s | 2 | ||||
| -rw-r--r-- | llvm/test/MC/Disassembler/AArch64/arm64-arithmetic.txt | 16 | ||||
| -rw-r--r-- | llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt | 12 |
7 files changed, 124 insertions, 41 deletions
diff --git a/llvm/test/MC/AArch64/arm64-aliases.s b/llvm/test/MC/AArch64/arm64-aliases.s index 1d7c48ca9b1..3ace7a0f718 100644 --- a/llvm/test/MC/AArch64/arm64-aliases.s +++ b/llvm/test/MC/AArch64/arm64-aliases.s @@ -134,18 +134,101 @@ foo: mov x0, #281470681743360 mov x0, #18446744073709486080 -; CHECK: movz x0, #0xffff, lsl #32 -; CHECK: movn x0, #0xffff +; CHECK: mov x0, #0xffff00000000 +; CHECK: mov x0, #-0x10000 mov w0, #0xffffffff mov w0, #0xffffff00 mov wzr, #0xffffffff mov wzr, #0xffffff00 -; CHECK: movn w0, #0 -; CHECK: movn w0, #0xff -; CHECK: movn wzr, #0 -; CHECK: movn wzr, #0xff +; CHECK: mov w0, #-0x1 +; CHECK: mov w0, #-0x100 +; CHECK: mov wzr, #-0x1 +; CHECK: mov wzr, #-0x100 + + ; 0 can be encoded by MOVZ in multiple ways, only "lsl #0" is a MOV alias. + movz x0, #0 + movz x0, #0, lsl #16 + movz x0, #0, lsl #32 + movz x0, #0, lsl #48 + movz w0, #0 + movz w0, #0, lsl #16 +; CHECK: mov x0, #0x0 +; CHECK: movz x0, #0x0, lsl #16 +; CHECK: movz x0, #0x0, lsl #32 +; CHECK: movz x0, #0x0, lsl #48 +; CHECK: mov w0, #0x0 +; CHECK: movz w0, #0x0, lsl #16 + + ; Similarly to MOVZ, -1 can be encoded in multiple ways, only one of which is + ; "MOV". + movn x0, #0 + movn x0, #0, lsl #16 + movn x0, #0, lsl #32 + movn x0, #0, lsl #48 + movn w0, #0 + movn w0, #0, lsl #16 +; CHECK: mov x0, #-0x1 +; CHECK: movn x0, #0x0, lsl #16 +; CHECK: movn x0, #0x0, lsl #32 +; CHECK: movn x0, #0x0, lsl #48 +; CHECK: mov w0, #-0x1 +; CHECK: movn w0, #0x0, lsl #16 + + ; Two 32-bit immediates are encodable by both MOVN and MOVZ, make sure the MOV + ; corresponds to the MOVZ version. + movz w0, #0xffff + movz w0, #0xffff, lsl #16 + movn w0, #0xffff + movn w0, #0xffff, lsl #16 +; CHECK: mov w0, #0xffff +; CHECK: mov w0, #-0x10000 +; CHECK: movn w0, #0xffff +; CHECK: movn w0, #0xffff, lsl #16 + + orr x20, xzr, #0xaaaaaaaaaaaaaaaa + orr w15, wzr, #0xaaaaaaaa +; CHECK: mov x20, #-0x5555555555555556 +; CHECK: mov w15, #-0x55555556 + + ; ORR is mostly repeating bit sequences and cannot encode -1, so it only + ; overlaps with MOVZ or MOVN if the repeat-width is the whole register. In + ; both cases MOVZ/MOVN are preferred. + orr x3, xzr, #0x1 + orr w3, wzr, #0x1 + orr x3, xzr, #0x10000 + orr w3, wzr, #0x10000 + orr x3, xzr, #0x700000000 + orr x3, xzr, #0x3000000000000 +; CHECK: orr x3, xzr, #0x1 +; CHECK: orr w3, wzr, #0x1 +; CHECK: orr x3, xzr, #0x10000 +; CHECK: orr w3, wzr, #0x10000 +; CHECK: orr x3, xzr, #0x700000000 +; CHECK: orr x3, xzr, #0x3000000000000 + + + orr x5, xzr, #0xfffffffffffffff0 + orr w2, wzr, #0xfffffffe + orr x5, xzr, #0xfffffffffcffffff + orr w2, wzr, #0xf0ffffff + orr x5, xzr, #0xffffff00ffffffff + orr x5, xzr, #0x8000ffffffffffff +; CHECK: orr x5, xzr, #0xfffffffffffffff0 +; CHECK: orr w2, wzr, #0xfffffffe +; CHECK: orr x5, xzr, #0x8000ffffffffffff + + ; 0xffff is interesting because there are exceptions in the MOVN rules for + ; it. Make sure we don't accidentally fall down any of those holes. + orr w3, wzr, #0xffff0000 + orr w3, wzr, #0xffff + orr x3, xzr, #0xffff000000000000 + orr x5, xzr, #0x0000ffffffffffff +; CHECK: orr w3, wzr, #0xffff0000 +; CHECK: orr w3, wzr, #0xffff +; CHECK: orr x3, xzr, #0xffff000000000000 +; CHECK: orr x5, xzr, #0xffffffffffff ;----------------------------------------------------------------------------- ; MVN aliases diff --git a/llvm/test/MC/AArch64/arm64-arithmetic-encoding.s b/llvm/test/MC/AArch64/arm64-arithmetic-encoding.s index 63532e6b798..7b090692de3 100644 --- a/llvm/test/MC/AArch64/arm64-arithmetic-encoding.s +++ b/llvm/test/MC/AArch64/arm64-arithmetic-encoding.s @@ -494,20 +494,20 @@ foo: movz w0, #1, lsl #16 movz x0, #1, lsl #16 -; CHECK: movz w0, #1 ; encoding: [0x20,0x00,0x80,0x52] -; CHECK: movz x0, #1 ; encoding: [0x20,0x00,0x80,0xd2] -; CHECK: movz w0, #1, lsl #16 ; encoding: [0x20,0x00,0xa0,0x52] -; CHECK: movz x0, #1, lsl #16 ; encoding: [0x20,0x00,0xa0,0xd2] +; CHECK: mov w0, #1 ; encoding: [0x20,0x00,0x80,0x52] +; CHECK: mov x0, #1 ; encoding: [0x20,0x00,0x80,0xd2] +; CHECK: mov w0, #65536 ; encoding: [0x20,0x00,0xa0,0x52] +; CHECK: mov x0, #65536 ; encoding: [0x20,0x00,0xa0,0xd2] movn w0, #2 movn x0, #2 movn w0, #2, lsl #16 movn x0, #2, lsl #16 -; CHECK: movn w0, #2 ; encoding: [0x40,0x00,0x80,0x12] -; CHECK: movn x0, #2 ; encoding: [0x40,0x00,0x80,0x92] -; CHECK: movn w0, #2, lsl #16 ; encoding: [0x40,0x00,0xa0,0x12] -; CHECK: movn x0, #2, lsl #16 ; encoding: [0x40,0x00,0xa0,0x92] +; CHECK: mov w0, #-3 ; encoding: [0x40,0x00,0x80,0x12] +; CHECK: mov x0, #-3 ; encoding: [0x40,0x00,0x80,0x92] +; CHECK: mov w0, #-131073 ; encoding: [0x40,0x00,0xa0,0x12] +; CHECK: mov x0, #-131073 ; encoding: [0x40,0x00,0xa0,0x92] movk w0, #1 movk x0, #1 diff --git a/llvm/test/MC/AArch64/basic-a64-instructions.s b/llvm/test/MC/AArch64/basic-a64-instructions.s index f8e49432145..69229848fde 100644 --- a/llvm/test/MC/AArch64/basic-a64-instructions.s +++ b/llvm/test/MC/AArch64/basic-a64-instructions.s @@ -3267,8 +3267,8 @@ _func: mov w3, #0xf000f mov x10, #0xaaaaaaaaaaaaaaaa -// CHECK: orr w3, wzr, #0xf000f // encoding: [0xe3,0x8f,0x00,0x32] -// CHECK: orr x10, xzr, #0xaaaaaaaaaaaaaaaa // encoding: [0xea,0xf3,0x01,0xb2] +// CHECK: mov w3, #983055 // encoding: [0xe3,0x8f,0x00,0x32] +// CHECK: mov x10, #-6148914691236517206 // encoding: [0xea,0xf3,0x01,0xb2] // The Imm field of logicalImm operations has to be truncated to the // register width, i.e. 32 bits @@ -3355,13 +3355,13 @@ _func: movz w1, #65535, lsl #0 movz w2, #0, lsl #16 movn w2, #1234, lsl #0 -// CHECK: movz w1, #{{65535|0xffff}} // encoding: [0xe1,0xff,0x9f,0x52] +// CHECK: mov w1, #65535 // encoding: [0xe1,0xff,0x9f,0x52] // CHECK: movz w2, #0, lsl #16 // encoding: [0x02,0x00,0xa0,0x52] -// CHECK: movn w2, #{{1234|0x4d2}} // encoding: [0x42,0x9a,0x80,0x12] +// CHECK: mov w2, #-1235 // encoding: [0x42,0x9a,0x80,0x12] movz x2, #1234, lsl #32 movk xzr, #4321, lsl #48 -// CHECK: movz x2, #{{1234|0x4d2}}, lsl #32 // encoding: [0x42,0x9a,0xc0,0xd2] +// CHECK: mov x2, #5299989643264 // encoding: [0x42,0x9a,0xc0,0xd2] // CHECK: movk xzr, #{{4321|0x10e1}}, lsl #48 // encoding: [0x3f,0x1c,0xe2,0xf2] movz x2, #:abs_g0:sym diff --git a/llvm/test/MC/AArch64/ldr-pseudo.s b/llvm/test/MC/AArch64/ldr-pseudo.s index 6a437f3cb36..6d2bbe8db16 100644 --- a/llvm/test/MC/AArch64/ldr-pseudo.s +++ b/llvm/test/MC/AArch64/ldr-pseudo.s @@ -8,17 +8,17 @@ // CHECK-LABEL: f1: f1: ldr x0, =0x1234 -// CHECK: movz x0, #0x1234 +// CHECK: mov x0, #0x1234 ldr w1, =0x4567 -// CHECK: movz w1, #0x4567 +// CHECK: mov w1, #0x4567 ldr x0, =0x12340000 -// CHECK: movz x0, #0x1234, lsl #16 +// CHECK: mov x0, #0x12340000 ldr w1, =0x45670000 -// CHECK: movz w1, #0x4567, lsl #16 +// CHECK: mov w1, #0x45670000 ldr x0, =0xabc00000000 -// CHECK: movz x0, #0xabc, lsl #32 +// CHECK: mov x0, #0xabc00000000 ldr x0, =0xbeef000000000000 -// CHECK: movz x0, #0xbeef, lsl #48 +// CHECK: mov x0, #-0x4111000000000000 .section b,"ax",@progbits // CHECK-LABEL: f3: @@ -128,7 +128,7 @@ f13: adds x0, x0, #1 adds x0, x0, #1 ldr w0, =0x101 -// CHECK: movz w0, #0x101 +// CHECK: mov w0, #0x101 adds x0, x0, #1 adds x0, x0, #1 ldr w0, =bar diff --git a/llvm/test/MC/AArch64/single-slash.s b/llvm/test/MC/AArch64/single-slash.s index c5a443001a7..83e87bc95d2 100644 --- a/llvm/test/MC/AArch64/single-slash.s +++ b/llvm/test/MC/AArch64/single-slash.s @@ -2,5 +2,5 @@ // Test that a single slash is not mistaken as the start of comment. -//CHECK: movz x0, #16 +//CHECK: mov x0, #16 movz x0, #(32 / 2) diff --git a/llvm/test/MC/Disassembler/AArch64/arm64-arithmetic.txt b/llvm/test/MC/Disassembler/AArch64/arm64-arithmetic.txt index 6ba474ff007..95b44858e84 100644 --- a/llvm/test/MC/Disassembler/AArch64/arm64-arithmetic.txt +++ b/llvm/test/MC/Disassembler/AArch64/arm64-arithmetic.txt @@ -452,20 +452,20 @@ 0x20 0x00 0xa0 0x52 0x20 0x00 0xa0 0xd2 -# CHECK: movz w0, #1 -# CHECK: movz x0, #1 -# CHECK: movz w0, #1, lsl #16 -# CHECK: movz x0, #1, lsl #16 +# CHECK: mov w0, #1 +# CHECK: mov x0, #1 +# CHECK: mov w0, #65536 +# CHECK: mov x0, #65536 0x40 0x00 0x80 0x12 0x40 0x00 0x80 0x92 0x40 0x00 0xa0 0x12 0x40 0x00 0xa0 0x92 -# CHECK: movn w0, #2 -# CHECK: movn x0, #2 -# CHECK: movn w0, #2, lsl #16 -# CHECK: movn x0, #2, lsl #16 +# CHECK: mov w0, #-3 +# CHECK: mov x0, #-3 +# CHECK: mov w0, #-131073 +# CHECK: mov x0, #-131073 0x20 0x00 0x80 0x72 0x20 0x00 0x80 0xf2 diff --git a/llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt b/llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt index 185f0c1124a..9d6723a96e4 100644 --- a/llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt +++ b/llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt @@ -2907,8 +2907,8 @@ 0x7f 0xf0 0x1 0xf2 0xff 0xf3 0x0 0xf2 -# CHECK: orr w3, wzr, #0xf000f -# CHECK: orr x10, xzr, #0xaaaaaaaaaaaaaaaa +# CHECK: mov w3, #983055 +# CHECK: mov x10, #-6148914691236517206 0xe3 0x8f 0x0 0x32 0xea 0xf3 0x1 0xb2 @@ -2991,19 +2991,19 @@ # limitation in InstAlias. Lots of the "mov[nz]" instructions should # be "mov". -# CHECK: movz w1, #{{65535|0xffff}} +# CHECK: mov w1, #{{65535|0xffff}} # CHECK: movz w2, #0, lsl #16 -# CHECK: movn w2, #{{1234|0x4d2}} +# CHECK: mov w2, #-1235 0xe1 0xff 0x9f 0x52 0x2 0x0 0xa0 0x52 0x42 0x9a 0x80 0x12 -# CHECK: movz x2, #{{1234|0x4d2}}, lsl #32 +# CHECK: mov x2, #5299989643264 # CHECK: movk xzr, #{{4321|0x10e1}}, lsl #48 0x42 0x9a 0xc0 0xd2 0x3f 0x1c 0xe2 0xf2 -# CHECK: movz x2, #0 +# CHECK: mov x2, #0 # CHECK: movk w3, #0 # CHECK: movz x4, #0, lsl #16 # CHECK: movk w5, #0, lsl #16 |
