diff options
Diffstat (limited to 'llvm/test/MC')
| -rw-r--r-- | llvm/test/MC/Disassembler/Mips/micromips32r6/valid.txt | 2 | ||||
| -rw-r--r-- | llvm/test/MC/Disassembler/Mips/micromips64r6/valid.txt | 2 | ||||
| -rw-r--r-- | llvm/test/MC/Mips/micromips/invalid.s | 8 | ||||
| -rw-r--r-- | llvm/test/MC/Mips/micromips32r6/invalid.s | 8 | ||||
| -rw-r--r-- | llvm/test/MC/Mips/micromips32r6/valid.s | 2 | ||||
| -rw-r--r-- | llvm/test/MC/Mips/micromips64r6/invalid.s | 8 | ||||
| -rw-r--r-- | llvm/test/MC/Mips/micromips64r6/valid.s | 2 |
7 files changed, 32 insertions, 0 deletions
diff --git a/llvm/test/MC/Disassembler/Mips/micromips32r6/valid.txt b/llvm/test/MC/Disassembler/Mips/micromips32r6/valid.txt index 38475325617..13a9abfee14 100644 --- a/llvm/test/MC/Disassembler/Mips/micromips32r6/valid.txt +++ b/llvm/test/MC/Disassembler/Mips/micromips32r6/valid.txt @@ -307,3 +307,5 @@ 0x00 0x65 0x10 0x90 # CHECK: srav $2, $3, $5 0x00 0x83 0x38 0x40 # CHECK: srl $4, $3, 7 0x00 0x65 0x10 0x50 # CHECK: srlv $2, $3, $5 +0x22 0x04 0x10 0x08 # CHECK: lwp $16, 8($4) +0x22 0x04 0x90 0x08 # CHECK: swp $16, 8($4) diff --git a/llvm/test/MC/Disassembler/Mips/micromips64r6/valid.txt b/llvm/test/MC/Disassembler/Mips/micromips64r6/valid.txt index 757e6e3d103..58e27a490e1 100644 --- a/llvm/test/MC/Disassembler/Mips/micromips64r6/valid.txt +++ b/llvm/test/MC/Disassembler/Mips/micromips64r6/valid.txt @@ -256,3 +256,5 @@ 0x58 0xa4 0x18 0x58 # CHECK: dmuh $3, $4, $5 0x58 0xa4 0x18 0x98 # CHECK: dmulu $3, $4, $5 0x58 0xa4 0x18 0xd8 # CHECK: dmuhu $3, $4, $5 +0x22 0x04 0x10 0x08 # CHECK: lwp $16, 8($4) +0x22 0x04 0x90 0x08 # CHECK: swp $16, 8($4) diff --git a/llvm/test/MC/Mips/micromips/invalid.s b/llvm/test/MC/Mips/micromips/invalid.s index f034f312d72..9ef6d865a77 100644 --- a/llvm/test/MC/Mips/micromips/invalid.s +++ b/llvm/test/MC/Mips/micromips/invalid.s @@ -83,3 +83,11 @@ she $4, 8($33) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset she $4, 512($5) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset she $4, -513($5) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset + lwp $31, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + # FIXME: This ought to point at the $34 but memory is treated as one operand. + lwp $16, 8($34) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 12-bit signed offset + lwp $16, 4096($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 12-bit signed offset + lwp $16, 8($16) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different + swp $31, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + swp $16, 8($34) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 12-bit signed offset + swp $16, 4096($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 12-bit signed offset diff --git a/llvm/test/MC/Mips/micromips32r6/invalid.s b/llvm/test/MC/Mips/micromips32r6/invalid.s index 7ebbc6fa320..ad1eb6ff251 100644 --- a/llvm/test/MC/Mips/micromips32r6/invalid.s +++ b/llvm/test/MC/Mips/micromips32r6/invalid.s @@ -188,3 +188,11 @@ swm32 $5, $6, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: $16 or $31 expected swm32 $16, $19, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers expected swm32 $16-$25, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand + lwp $31, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + # FIXME: This ought to point at the $34 but memory is treated as one operand. + lwp $16, 8($34) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 12-bit signed offset + lwp $16, 4096($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 12-bit signed offset + lwp $16, 8($16) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different + swp $31, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + swp $16, 8($34) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 12-bit signed offset + swp $16, 4096($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 12-bit signed offset diff --git a/llvm/test/MC/Mips/micromips32r6/valid.s b/llvm/test/MC/Mips/micromips32r6/valid.s index 23cd4275377..041915711a4 100644 --- a/llvm/test/MC/Mips/micromips32r6/valid.s +++ b/llvm/test/MC/Mips/micromips32r6/valid.s @@ -327,3 +327,5 @@ sll $3, 7 # CHECK: sll $3, $3, 7 # encoding: [0x00,0x63,0x38,0x00] sra $3, 7 # CHECK: sra $3, $3, 7 # encoding: [0x00,0x63,0x38,0x80] srl $3, 7 # CHECK: srl $3, $3, 7 # encoding: [0x00,0x63,0x38,0x40] + lwp $16, 8($4) # CHECK: lwp $16, 8($4) # encoding: [0x22,0x04,0x10,0x08] + swp $16, 8($4) # CHECK: swp $16, 8($4) # encoding: [0x22,0x04,0x90,0x08] diff --git a/llvm/test/MC/Mips/micromips64r6/invalid.s b/llvm/test/MC/Mips/micromips64r6/invalid.s index 34995dda42e..c1c00dc5edf 100644 --- a/llvm/test/MC/Mips/micromips64r6/invalid.s +++ b/llvm/test/MC/Mips/micromips64r6/invalid.s @@ -220,3 +220,11 @@ swm32 $5, $6, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: $16 or $31 expected swm32 $16, $19, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers expected swm32 $16-$25, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand + lwp $31, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + # FIXME: This ought to point at the $34 but memory is treated as one operand. + lwp $16, 8($34) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 12-bit signed offset + lwp $16, 4096($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 12-bit signed offset + lwp $16, 8($16) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different + swp $31, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + swp $16, 8($34) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 12-bit signed offset + swp $16, 4096($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 12-bit signed offset diff --git a/llvm/test/MC/Mips/micromips64r6/valid.s b/llvm/test/MC/Mips/micromips64r6/valid.s index 45172a796e9..b08bb7b5f62 100644 --- a/llvm/test/MC/Mips/micromips64r6/valid.s +++ b/llvm/test/MC/Mips/micromips64r6/valid.s @@ -259,5 +259,7 @@ a: dmuh $3, $4, $5 # CHECK dmuh $3, $4, $5 # encoding: [0x58,0xa4,0x18,0x58] dmulu $3, $4, $5 # CHECK dmulu $3, $4, $5 # encoding: [0x58,0xa4,0x18,0x98] dmuhu $3, $4, $5 # CHECK dmuhu $3, $4, $5 # encoding: [0x58,0xa4,0x18,0xd8] + lwp $16, 8($4) # CHECK: lwp $16, 8($4) # encoding: [0x22,0x04,0x10,0x08] + swp $16, 8($4) # CHECK: swp $16, 8($4) # encoding: [0x22,0x04,0x90,0x08] 1: |
