diff options
Diffstat (limited to 'llvm/test/MC')
| -rw-r--r-- | llvm/test/MC/ARM/diagnostics.s | 7 | ||||
| -rw-r--r-- | llvm/test/MC/Disassembler/ARM/unpredictable-MVN-arm.txt | 38 |
2 files changed, 45 insertions, 0 deletions
diff --git a/llvm/test/MC/ARM/diagnostics.s b/llvm/test/MC/ARM/diagnostics.s index 42e8b6a6128..899c8112940 100644 --- a/llvm/test/MC/ARM/diagnostics.s +++ b/llvm/test/MC/ARM/diagnostics.s @@ -742,3 +742,10 @@ foo2: adds r0 @ CHECK-ERRORS: error: too few operands for instruction @ CHECK-ERRORS: error: too few operands for instruction + + @ Using pc for MVN + mvn pc, r6, lsl r7 +@ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this: +@ CHECK-ERRORS: note: operand must be a register in range [r0, r14] +@ CHECK-ERRORS: mvn pc, r6, lsl r7 +@ CHECK-ERRORS: ^ diff --git a/llvm/test/MC/Disassembler/ARM/unpredictable-MVN-arm.txt b/llvm/test/MC/Disassembler/ARM/unpredictable-MVN-arm.txt new file mode 100644 index 00000000000..ef52dee34c9 --- /dev/null +++ b/llvm/test/MC/Disassembler/ARM/unpredictable-MVN-arm.txt @@ -0,0 +1,38 @@ +# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi 2>&1 | FileCheck %s + +# A8.8.116 MVN (register) +# MVN(S)<c> <Rd>, <Rm>{, <shift>} +# +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | cond | 0 0| 0| 1 1 1 1| S|(0)(0)(0)(0)| Rd | imm5 |type | 0| Rm | +# ------------------------------------------------------------------------------------------------- + +# MVN r2, r3 ; with bit 16 == 1 => Unpredictable +# CHECK: potentially undefined +# CHECK: 0x03 0x20 0xe1 0xe1 +0x03 0x20 0xe1 0xe1 + +# A8.8.117 MVN (register-shifted register) +# MVN(S)<c> <Rd>, <Rm>, <type> <Rs> +# +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | cond | 0 0| 0| 1 1 1 1| S|(0)(0)(0)(0)| Rd | Rs | 0|type | 1| Rm | +# ------------------------------------------------------------------------------------------------- +# if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; + +# MVN r5, pc, lsl r7 +# CHECK: potentially undefined +# CHECK: 0x1f 0x57 0xe0 0xe1 +0x1f 0x57 0xe0 0xe1 + +# MVN pc, r6, lsl r7 +# CHECK: potentially undefined +# CHECK: 0x16 0xf7 0xe0 0xe1 +0x16 0xf7 0xe0 0xe1 + +# MVN r5, r6, lsl pc +# CHECK: potentially undefined +# CHECK: 0x16 0x5f 0xe0 0xe1 +0x16 0x5f 0xe0 0xe1 |
