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-rw-r--r--llvm/test/MC/Disassembler/Mips/crc/valid-32r6-el.txt9
-rw-r--r--llvm/test/MC/Disassembler/Mips/crc/valid-32r6.txt9
-rw-r--r--llvm/test/MC/Disassembler/Mips/crc/valid-64r6-el.txt11
-rw-r--r--llvm/test/MC/Disassembler/Mips/crc/valid-64r6.txt11
-rw-r--r--llvm/test/MC/Mips/crc/invalid.s65
-rw-r--r--llvm/test/MC/Mips/crc/invalid64.s24
-rw-r--r--llvm/test/MC/Mips/crc/module-crc.s22
-rw-r--r--llvm/test/MC/Mips/crc/module-nocrc.s21
-rw-r--r--llvm/test/MC/Mips/crc/set-crc-directive.s7
-rw-r--r--llvm/test/MC/Mips/crc/set-nocrc-directive.s9
-rw-r--r--llvm/test/MC/Mips/crc/valid.s12
-rw-r--r--llvm/test/MC/Mips/crc/valid64.s6
12 files changed, 206 insertions, 0 deletions
diff --git a/llvm/test/MC/Disassembler/Mips/crc/valid-32r6-el.txt b/llvm/test/MC/Disassembler/Mips/crc/valid-32r6-el.txt
new file mode 100644
index 00000000000..7a335b965fa
--- /dev/null
+++ b/llvm/test/MC/Disassembler/Mips/crc/valid-32r6-el.txt
@@ -0,0 +1,9 @@
+# RUN: llvm-mc --disassemble %s -triple=mipsel-unknown-linux-gnu \
+# RUN: -mcpu=mips32r6 -mattr=+crc | FileCheck %s
+
+0x0f 0x00 0x41 0x7c # CHECK: crc32b $1, $2, $1
+0x4f 0x00 0xa4 0x7c # CHECK: crc32h $4, $5, $4
+0x8f 0x00 0x07 0x7d # CHECK: crc32w $7, $8, $7
+0x0f 0x01 0x41 0x7c # CHECK: crc32cb $1, $2, $1
+0x4f 0x01 0xa4 0x7c # CHECK: crc32ch $4, $5, $4
+0x8f 0x01 0x07 0x7d # CHECK: crc32cw $7, $8, $7
diff --git a/llvm/test/MC/Disassembler/Mips/crc/valid-32r6.txt b/llvm/test/MC/Disassembler/Mips/crc/valid-32r6.txt
new file mode 100644
index 00000000000..a14c8e78d86
--- /dev/null
+++ b/llvm/test/MC/Disassembler/Mips/crc/valid-32r6.txt
@@ -0,0 +1,9 @@
+# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux-gnu \
+# RUN: -mcpu=mips32r6 -mattr=+crc | FileCheck %s
+
+0x7c 0x41 0x00 0x0f # CHECK: crc32b $1, $2, $1
+0x7c 0xa4 0x00 0x4f # CHECK: crc32h $4, $5, $4
+0x7d 0x07 0x00 0x8f # CHECK: crc32w $7, $8, $7
+0x7c 0x41 0x01 0x0f # CHECK: crc32cb $1, $2, $1
+0x7c 0xa4 0x01 0x4f # CHECK: crc32ch $4, $5, $4
+0x7d 0x07 0x01 0x8f # CHECK: crc32cw $7, $8, $7
diff --git a/llvm/test/MC/Disassembler/Mips/crc/valid-64r6-el.txt b/llvm/test/MC/Disassembler/Mips/crc/valid-64r6-el.txt
new file mode 100644
index 00000000000..48c56aa994a
--- /dev/null
+++ b/llvm/test/MC/Disassembler/Mips/crc/valid-64r6-el.txt
@@ -0,0 +1,11 @@
+# RUN: llvm-mc --disassemble %s -triple=mips64el-unknown-linux-gnu \
+# RUN: -mcpu=mips64r6 -mattr=+crc | FileCheck %s
+
+0x0f 0x00 0x41 0x7c # CHECK: crc32b $1, $2, $1
+0x4f 0x00 0xa4 0x7c # CHECK: crc32h $4, $5, $4
+0x8f 0x00 0x07 0x7d # CHECK: crc32w $7, $8, $7
+0xcf 0x00 0x6a 0x7d # CHECK: crc32d $10, $11, $10
+0x0f 0x01 0x41 0x7c # CHECK: crc32cb $1, $2, $1
+0x4f 0x01 0xa4 0x7c # CHECK: crc32ch $4, $5, $4
+0x8f 0x01 0x07 0x7d # CHECK: crc32cw $7, $8, $7
+0xcf 0x01 0x6a 0x7d # CHECK: crc32cd $10, $11, $10
diff --git a/llvm/test/MC/Disassembler/Mips/crc/valid-64r6.txt b/llvm/test/MC/Disassembler/Mips/crc/valid-64r6.txt
new file mode 100644
index 00000000000..8be8223e3e2
--- /dev/null
+++ b/llvm/test/MC/Disassembler/Mips/crc/valid-64r6.txt
@@ -0,0 +1,11 @@
+# RUN: llvm-mc --disassemble %s -triple=mips64-unknown-linux-gnu \
+# RUN: -mcpu=mips64r6 -mattr=+crc | FileCheck %s
+
+0x7c 0x41 0x00 0x0f # CHECK: crc32b $1, $2, $1
+0x7c 0xa4 0x00 0x4f # CHECK: crc32h $4, $5, $4
+0x7d 0x07 0x00 0x8f # CHECK: crc32w $7, $8, $7
+0x7d 0x6a 0x00 0xcf # CHECK: crc32d $10, $11, $10
+0x7c 0x41 0x01 0x0f # CHECK: crc32cb $1, $2, $1
+0x7c 0xa4 0x01 0x4f # CHECK: crc32ch $4, $5, $4
+0x7d 0x07 0x01 0x8f # CHECK: crc32cw $7, $8, $7
+0x7d 0x6a 0x01 0xcf # CHECK: crc32cd $10, $11, $10
diff --git a/llvm/test/MC/Mips/crc/invalid.s b/llvm/test/MC/Mips/crc/invalid.s
new file mode 100644
index 00000000000..f8e0fba7da0
--- /dev/null
+++ b/llvm/test/MC/Mips/crc/invalid.s
@@ -0,0 +1,65 @@
+# Instructions that are invalid.
+#
+# RUN: not llvm-mc %s -arch=mips -mcpu=mips32r6 -mattr=+crc 2>%t1
+# RUN: FileCheck %s < %t1
+# RUN: not llvm-mc %s -arch=mips64 -mcpu=mips64r6 -mattr=+crc 2>%t1
+# RUN: FileCheck %s < %t1
+
+ .set noat
+ crc32b $1, $2, $2 # CHECK: :[[@LINE]]:3: error: source and destination must match
+ crc32b $1, $2, $3 # CHECK: :[[@LINE]]:3: error: source and destination must match
+ crc32b $1, $2, 2 # CHECK: :[[@LINE]]:19: error: invalid operand for instruction
+ crc32b $1, 2, $2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction
+ crc32b 1, $2, $2 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
+ crc32b $1, $2 # CHECK: :[[@LINE]]:3: error: too few operands for instruction
+ crc32b $1 # CHECK: :[[@LINE]]:3: error: too few operands for instruction
+ crc32b $1, $2, 0($2) # CHECK: :[[@LINE]]:19: error: invalid operand for instruction
+
+ crc32h $1, $2, $2 # CHECK: :[[@LINE]]:3: error: source and destination must match
+ crc32h $1, $2, $3 # CHECK: :[[@LINE]]:3: error: source and destination must match
+ crc32h $1, $2, 2 # CHECK: :[[@LINE]]:19: error: invalid operand for instruction
+ crc32h $1, 2, $2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction
+ crc32h 1, $2, $2 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
+ crc32h $1, $2 # CHECK: :[[@LINE]]:3: error: too few operands for instruction
+ crc32h $1 # CHECK: :[[@LINE]]:3: error: too few operands for instruction
+ crc32h $1, $2, 0($2) # CHECK: :[[@LINE]]:19: error: invalid operand for instruction
+
+ crc32w $1, $2, $2 # CHECK: :[[@LINE]]:3: error: source and destination must match
+ crc32w $1, $2, $3 # CHECK: :[[@LINE]]:3: error: source and destination must match
+ crc32w $1, $2, 2 # CHECK: :[[@LINE]]:19: error: invalid operand for instruction
+ crc32w $1, 2, $2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction
+ crc32w 1, $2, $2 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
+ crc32w $1, $2 # CHECK: :[[@LINE]]:3: error: too few operands for instruction
+ crc32w $1 # CHECK: :[[@LINE]]:3: error: too few operands for instruction
+ crc32w $1, $2, 0($2) # CHECK: :[[@LINE]]:19: error: invalid operand for instruction
+
+ crc32cb $1, $2, $2 # CHECK: :[[@LINE]]:3: error: source and destination must match
+ crc32cb $1, $2, $3 # CHECK: :[[@LINE]]:3: error: source and destination must match
+ crc32cb $1, $2, 2 # CHECK: :[[@LINE]]:20: error: invalid operand for instruction
+ crc32cb $1, 2, $2 # CHECK: :[[@LINE]]:16: error: invalid operand for instruction
+ crc32cb 1, $2, $2 # CHECK: :[[@LINE]]:12: error: invalid operand for instruction
+ crc32cb $1, $2 # CHECK: :[[@LINE]]:3: error: too few operands for instruction
+ crc32cb $1 # CHECK: :[[@LINE]]:3: error: too few operands for instruction
+ crc32cb $1, $2, 0($2) # CHECK: :[[@LINE]]:20: error: invalid operand for instruction
+
+ crc32ch $1, $2, $2 # CHECK: :[[@LINE]]:3: error: source and destination must match
+ crc32ch $1, $2, $3 # CHECK: :[[@LINE]]:3: error: source and destination must match
+ crc32ch $1, $2, 2 # CHECK: :[[@LINE]]:20: error: invalid operand for instruction
+ crc32ch $1, 2, $2 # CHECK: :[[@LINE]]:16: error: invalid operand for instruction
+ crc32ch 1, $2, $2 # CHECK: :[[@LINE]]:12: error: invalid operand for instruction
+ crc32ch $1, $2 # CHECK: :[[@LINE]]:3: error: too few operands for instruction
+ crc32ch $1 # CHECK: :[[@LINE]]:3: error: too few operands for instruction
+ crc32ch $1, $2, 0($2) # CHECK: :[[@LINE]]:20: error: invalid operand for instruction
+
+ crc32cw $1, $2, $2 # CHECK: :[[@LINE]]:3: error: source and destination must match
+ crc32cw $1, $2, $3 # CHECK: :[[@LINE]]:3: error: source and destination must match
+ crc32cw $1, $2, 2 # CHECK: :[[@LINE]]:20: error: invalid operand for instruction
+ crc32cw $1, 2, $2 # CHECK: :[[@LINE]]:16: error: invalid operand for instruction
+ crc32cw 1, $2, $2 # CHECK: :[[@LINE]]:12: error: invalid operand for instruction
+ crc32cw $1, $2 # CHECK: :[[@LINE]]:3: error: too few operands for instruction
+ crc32cw $1 # CHECK: :[[@LINE]]:3: error: too few operands for instruction
+ crc32cw $1, $2, 0($2) # CHECK: :[[@LINE]]:20: error: invalid operand for instruction
+
+ crc32 $1, $2, $2 # CHECK: :[[@LINE]]:3: error: unknown instruction
+ crcb $1, $2, $2 # CHECK: :[[@LINE]]:3: error: unknown instruction
+ crc $1, $2, $2 # CHECK: :[[@LINE]]:3: error: unknown instruction
diff --git a/llvm/test/MC/Mips/crc/invalid64.s b/llvm/test/MC/Mips/crc/invalid64.s
new file mode 100644
index 00000000000..239f5800391
--- /dev/null
+++ b/llvm/test/MC/Mips/crc/invalid64.s
@@ -0,0 +1,24 @@
+# Instructions that are invalid.
+#
+# RUN: not llvm-mc %s -triple=mips64-unknown-linux-gnu -mcpu=mips64r6 \
+# RUN: -mattr=+crc 2>%t1
+# RUN: FileCheck %s < %t1
+
+ .set noat
+ crc32d $1, $2, $2 # CHECK: :[[@LINE]]:3: error: source and destination must match
+ crc32d $1, $2, $3 # CHECK: :[[@LINE]]:3: error: source and destination must match
+ crc32d $1, $2, 2 # CHECK: :[[@LINE]]:18: error: invalid operand for instruction
+ crc32d $1, 2, $2 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
+ crc32d 1, $2, $2 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
+ crc32d $1, $2 # CHECK: :[[@LINE]]:3: error: too few operands for instruction
+ crc32d $1 # CHECK: :[[@LINE]]:3: error: too few operands for instruction
+ crc32d $1, $2, 0($2) # CHECK: :[[@LINE]]:18: error: invalid operand for instruction
+
+ crc32cd $1, $2, $2 # CHECK: :[[@LINE]]:3: error: source and destination must match
+ crc32cd $1, $2, $3 # CHECK: :[[@LINE]]:3: error: source and destination must match
+ crc32cd $1, $2, 2 # CHECK: :[[@LINE]]:19: error: invalid operand for instruction
+ crc32cd $1, 2, $2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction
+ crc32cd 1, $2, $2 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
+ crc32cd $1, $2 # CHECK: :[[@LINE]]:3: error: too few operands for instruction
+ crc32cd $1 # CHECK: :[[@LINE]]:3: error: too few operands for instruction
+ crc32cd $1, $2, 0($2) # CHECK: :[[@LINE]]:19: error: invalid operand for instruction
diff --git a/llvm/test/MC/Mips/crc/module-crc.s b/llvm/test/MC/Mips/crc/module-crc.s
new file mode 100644
index 00000000000..6d00c52e902
--- /dev/null
+++ b/llvm/test/MC/Mips/crc/module-crc.s
@@ -0,0 +1,22 @@
+# RUN: llvm-mc %s -triple=mips-unknown-linux-gnu -mcpu=mips32r6 | \
+# RUN: FileCheck %s -check-prefix=CHECK-ASM
+#
+# RUN: llvm-mc %s -triple=mips-unknown-linux-gnu -mcpu=mips32r6 \
+# RUN: -filetype=obj -o - | \
+# RUN: llvm-readobj -mips-abi-flags - | \
+# RUN: FileCheck %s -check-prefix=CHECK-OBJ
+
+# CHECK-ASM: .module crc
+
+# Check if the MIPS.abiflags section was correctly emitted:
+# CHECK-OBJ: MIPS ABI Flags {
+# CHECK-OBJ: ASEs [ (0x8000)
+# CHECK-OBJ: CRC (0x8000)
+# CHECK-OBJ: }
+
+ .module crc
+ crc32b $2,$3,$2
+
+# FIXME: Test should include gnu_attributes directive when implemented.
+# An explicit .gnu_attribute must be checked against the effective
+# command line options and any inconsistencies reported via a warning.
diff --git a/llvm/test/MC/Mips/crc/module-nocrc.s b/llvm/test/MC/Mips/crc/module-nocrc.s
new file mode 100644
index 00000000000..19020570ac9
--- /dev/null
+++ b/llvm/test/MC/Mips/crc/module-nocrc.s
@@ -0,0 +1,21 @@
+# RUN: llvm-mc %s -arch=mips -mcpu=mips32r6 -mattr=+crc | \
+# RUN: FileCheck %s -check-prefix=CHECK-ASM
+#
+# RUN: llvm-mc %s -arch=mips -mcpu=mips32r6 -filetype=obj -o - -mattr=+crc | \
+# RUN: llvm-readobj -mips-abi-flags - | \
+# RUN: FileCheck %s -check-prefix=CHECK-OBJ
+
+# CHECK-ASM: .module nocrc
+
+# Check that MIPS.abiflags has no CRC flag.
+# CHECK-OBJ: MIPS ABI Flags {
+# CHECK-OBJ: ASEs [ (0x0)
+# CHECK-OBJ-NOT: ASEs [ (0x8000)
+# CHECK-OBJ-NOT: CRC (0x8000)
+# CHECK-OBJ: }
+
+ .module nocrc
+
+# FIXME: Test should include gnu_attributes directive when implemented.
+# An explicit .gnu_attribute must be checked against the effective
+# command line options and any inconsistencies reported via a warning.
diff --git a/llvm/test/MC/Mips/crc/set-crc-directive.s b/llvm/test/MC/Mips/crc/set-crc-directive.s
new file mode 100644
index 00000000000..ab417ac7bb1
--- /dev/null
+++ b/llvm/test/MC/Mips/crc/set-crc-directive.s
@@ -0,0 +1,7 @@
+# RUN: llvm-mc %s -show-encoding -triple=mips-unknown-linux-gnu \
+# RUN: -mcpu=mips32r6 | FileCheck %s
+# RUN: llvm-mc %s -show-encoding -triple=mips64-unknown-linux-gnu \
+# RUN: -mcpu=mips64r6 | FileCheck %s
+
+ .set crc
+ crc32b $1, $2, $1 # CHECK: crc32b $1, $2, $1 # encoding: [0x7c,0x41,0x00,0x0f]
diff --git a/llvm/test/MC/Mips/crc/set-nocrc-directive.s b/llvm/test/MC/Mips/crc/set-nocrc-directive.s
new file mode 100644
index 00000000000..e89b7d9994d
--- /dev/null
+++ b/llvm/test/MC/Mips/crc/set-nocrc-directive.s
@@ -0,0 +1,9 @@
+# RUN: not llvm-mc %s -triple=mips-unknown-linux-gnu -show-encoding \
+# RUN: -mcpu=mips32r6 -mattr=+crc 2>%t1
+# RUN: FileCheck %s < %t1
+# RUN: not llvm-mc %s -triple=mips64-unknown-linux-gnu -show-encoding \
+# RUN: -mcpu=mips64r6 -mattr=+crc 2>%t1
+# RUN: FileCheck %s < %t1
+
+ .set nocrc
+ crc32b $1, $2, $1 # CHECK: instruction requires a CPU feature not currently enabled
diff --git a/llvm/test/MC/Mips/crc/valid.s b/llvm/test/MC/Mips/crc/valid.s
new file mode 100644
index 00000000000..52539a3ec64
--- /dev/null
+++ b/llvm/test/MC/Mips/crc/valid.s
@@ -0,0 +1,12 @@
+# RUN: llvm-mc %s -triple=mips-unknown-linux-gnu -show-encoding \
+# RUN: -mcpu=mips32r6 -mattr=+crc | FileCheck %s
+# RUN: llvm-mc %s -triple=mips64-unknown-linux-gnu -show-encoding \
+# RUN: -mcpu=mips64r6 -mattr=+crc | FileCheck %s
+
+ .set noat
+ crc32b $1, $2, $1 # CHECK: crc32b $1, $2, $1 # encoding: [0x7c,0x41,0x00,0x0f]
+ crc32h $4, $5, $4 # CHECK: crc32h $4, $5, $4 # encoding: [0x7c,0xa4,0x00,0x4f]
+ crc32w $7, $8, $7 # CHECK: crc32w $7, $8, $7 # encoding: [0x7d,0x07,0x00,0x8f]
+ crc32cb $1, $2, $1 # CHECK: crc32cb $1, $2, $1 # encoding: [0x7c,0x41,0x01,0x0f]
+ crc32ch $4, $5, $4 # CHECK: crc32ch $4, $5, $4 # encoding: [0x7c,0xa4,0x01,0x4f]
+ crc32cw $7, $8, $7 # CHECK: crc32cw $7, $8, $7 # encoding: [0x7d,0x07,0x01,0x8f]
diff --git a/llvm/test/MC/Mips/crc/valid64.s b/llvm/test/MC/Mips/crc/valid64.s
new file mode 100644
index 00000000000..0b8fe4f4df4
--- /dev/null
+++ b/llvm/test/MC/Mips/crc/valid64.s
@@ -0,0 +1,6 @@
+# RUN: llvm-mc %s -triple=mips64-unknown-linux-gnu -show-encoding \
+# RUN: -mcpu=mips64r6 -mattr=+crc | FileCheck %s
+
+ .set noat
+ crc32d $10, $11, $10 # CHECK: crc32d $10, $11, $10 # encoding: [0x7d,0x6a,0x00,0xcf]
+ crc32cd $10, $11, $10 # CHECK: crc32cd $10, $11, $10 # encoding: [0x7d,0x6a,0x01,0xcf]
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