diff options
Diffstat (limited to 'llvm/test/MC/Mips/mips2')
-rw-r--r-- | llvm/test/MC/Mips/mips2/invalid-mips3-wrong-error.s | 4 | ||||
-rw-r--r-- | llvm/test/MC/Mips/mips2/invalid-mips3.s | 4 | ||||
-rw-r--r-- | llvm/test/MC/Mips/mips2/invalid-mips4-wrong-error.s | 3 | ||||
-rw-r--r-- | llvm/test/MC/Mips/mips2/invalid-mips4.s | 3 |
4 files changed, 7 insertions, 7 deletions
diff --git a/llvm/test/MC/Mips/mips2/invalid-mips3-wrong-error.s b/llvm/test/MC/Mips/mips2/invalid-mips3-wrong-error.s index d9533fb392d..9aa17b6695b 100644 --- a/llvm/test/MC/Mips/mips2/invalid-mips3-wrong-error.s +++ b/llvm/test/MC/Mips/mips2/invalid-mips3-wrong-error.s @@ -7,12 +7,8 @@ .set noat dmult $s7,$a5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - ld $sp,-28645($s1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction ldl $t8,-4167($t8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction ldr $t2,-30358($s4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - lld $zero,-14736($ra) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset - lwu $s3,-24086($v1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction scd $t3,-8243($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset - sd $t0,5835($a6) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction sdl $a3,-20961($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction sdr $a7,-20423($t0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction diff --git a/llvm/test/MC/Mips/mips2/invalid-mips3.s b/llvm/test/MC/Mips/mips2/invalid-mips3.s index 67f9d539984..80a09673413 100644 --- a/llvm/test/MC/Mips/mips2/invalid-mips3.s +++ b/llvm/test/MC/Mips/mips2/invalid-mips3.s @@ -50,7 +50,11 @@ eret # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled floor.l.d $f26,$f7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled floor.l.s $f12,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + ld $sp,-28645($s1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset + lld $zero,-14736($ra) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset + lwu $s3,-24086($v1) # CHECK: :[[@LINE]]:24: error: expected memory with 12-bit signed offset round.l.d $f12,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled round.l.s $f25,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + sd $t0,5835($a6) # CHECK: :[[@LINE]]:24: error: expected memory with 16-bit signed offset trunc.l.d $f23,$f23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled trunc.l.s $f28,$f31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/llvm/test/MC/Mips/mips2/invalid-mips4-wrong-error.s b/llvm/test/MC/Mips/mips2/invalid-mips4-wrong-error.s index 6542b35ce4c..ef5657833ca 100644 --- a/llvm/test/MC/Mips/mips2/invalid-mips4-wrong-error.s +++ b/llvm/test/MC/Mips/mips2/invalid-mips4-wrong-error.s @@ -8,9 +8,6 @@ .set noat bc1fl $fcc7,27 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction bc1tl $fcc7,27 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - ld $sp,-28645($s1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - lwu $s3,-24086($v1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction scd $15,-8243($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset - sd $12,5835($10) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction sdl $a3,-20961($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction sdr $11,-20423($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction diff --git a/llvm/test/MC/Mips/mips2/invalid-mips4.s b/llvm/test/MC/Mips/mips2/invalid-mips4.s index 13923f01df8..fb9da85fd20 100644 --- a/llvm/test/MC/Mips/mips2/invalid-mips4.s +++ b/llvm/test/MC/Mips/mips2/invalid-mips4.s @@ -48,6 +48,7 @@ floor.l.s $f12,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled ldxc1 $f8,$s7($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled lwxc1 $f12,$s1($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + lwu $s3,-24086($v1) # CHECK: :[[@LINE]]:23: error: expected memory with 12-bit signed offset movf $gp,$8,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movf $gp,$8,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction movf.d $f6,$f11,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled @@ -65,8 +66,10 @@ movz $a1,$s6,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movz.d $f12,$f29,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movz.s $f25,$f7,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + ld $sp,-28645($s1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset round.l.d $f12,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled round.l.s $f25,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + sd $12,5835($10) # CHECK: :[[@LINE]]:23: error: expected memory with 16-bit signed offset sdxc1 $f11,$10($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled trunc.l.d $f23,$f23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled trunc.l.s $f28,$f31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled |