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-rw-r--r--llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ps.live.ll5
-rw-r--r--llvm/test/CodeGen/AMDGPU/macro-fusion-cluster-vcc-uses.mir34
-rw-r--r--llvm/test/CodeGen/AMDGPU/shrink-carry.mir16
-rw-r--r--llvm/test/CodeGen/AMDGPU/shrink-vop3-carry-out.mir8
4 files changed, 33 insertions, 30 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ps.live.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ps.live.ll
index 1c3cba8d3e4..3061bd91c9c 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ps.live.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ps.live.ll
@@ -1,7 +1,10 @@
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck %s
; CHECK-LABEL: {{^}}test1:
-; CHECK: v_cndmask_b32_e64 v0, 0, 1, exec
+; CHECK: s_mov_b64 s[0:1], exec
+; CHECK: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
+;
+; Note: The hardware doesn't implement EXEC as src2 for v_cndmask.
;
; Note: We could generate better code here if we recognized earlier that
; there is no WQM use and therefore llvm.amdgcn.ps.live is constant. However,
diff --git a/llvm/test/CodeGen/AMDGPU/macro-fusion-cluster-vcc-uses.mir b/llvm/test/CodeGen/AMDGPU/macro-fusion-cluster-vcc-uses.mir
index 2a431fe7946..dff9024df62 100644
--- a/llvm/test/CodeGen/AMDGPU/macro-fusion-cluster-vcc-uses.mir
+++ b/llvm/test/CodeGen/AMDGPU/macro-fusion-cluster-vcc-uses.mir
@@ -9,9 +9,9 @@ registers:
- { id: 0, class: vgpr_32 }
- { id: 1, class: vgpr_32 }
- { id: 2, class: vgpr_32 }
- - { id: 3, class: sreg_64 }
+ - { id: 3, class: sreg_64_xexec }
- { id: 4, class: vgpr_32 }
- - { id: 5, class: sreg_64 }
+ - { id: 5, class: sreg_64_xexec }
- { id: 6, class: vgpr_32 }
- { id: 7, class: vgpr_32 }
@@ -42,13 +42,13 @@ registers:
- { id: 6, class: vgpr_32 }
- { id: 7, class: vgpr_32 }
- { id: 8, class: vgpr_32 }
- - { id: 9, class: sreg_64 }
+ - { id: 9, class: sreg_64_xexec }
- { id: 10, class: vgpr_32 }
- - { id: 11, class: sreg_64 }
+ - { id: 11, class: sreg_64_xexec }
- { id: 12, class: vgpr_32 }
- - { id: 13, class: sreg_64 }
+ - { id: 13, class: sreg_64_xexec }
- { id: 14, class: vgpr_32 }
- - { id: 15, class: sreg_64 }
+ - { id: 15, class: sreg_64_xexec }
body: |
bb.0:
@@ -77,9 +77,9 @@ name: cluster_mov_addc
registers:
- { id: 0, class: vgpr_32 }
- { id: 1, class: vgpr_32 }
- - { id: 2, class: sreg_64 }
+ - { id: 2, class: sreg_64_xexec }
- { id: 3, class: vgpr_32 }
- - { id: 4, class: sreg_64 }
+ - { id: 4, class: sreg_64_xexec }
- { id: 6, class: vgpr_32 }
- { id: 7, class: vgpr_32 }
@@ -104,12 +104,12 @@ registers:
- { id: 0, class: vgpr_32 }
- { id: 1, class: vgpr_32 }
- { id: 2, class: vgpr_32 }
- - { id: 3, class: sreg_64 }
+ - { id: 3, class: sreg_64_xexec }
- { id: 4, class: vgpr_32 }
- - { id: 5, class: sreg_64 }
+ - { id: 5, class: sreg_64_xexec }
- { id: 6, class: vgpr_32 }
- { id: 7, class: vgpr_32 }
- - { id: 8, class: sreg_64 }
+ - { id: 8, class: sreg_64_xexec }
body: |
bb.0:
%0 = V_MOV_B32_e32 0, implicit %exec
@@ -130,9 +130,9 @@ registers:
- { id: 0, class: vgpr_32 }
- { id: 1, class: vgpr_32 }
- { id: 2, class: vgpr_32 }
- - { id: 3, class: sreg_64 }
+ - { id: 3, class: sreg_64_xexec }
- { id: 4, class: vgpr_32 }
- - { id: 5, class: sreg_64 }
+ - { id: 5, class: sreg_64_xexec }
- { id: 6, class: vgpr_32 }
- { id: 7, class: vgpr_32 }
@@ -156,9 +156,9 @@ registers:
- { id: 0, class: vgpr_32 }
- { id: 1, class: vgpr_32 }
- { id: 2, class: vgpr_32 }
- - { id: 3, class: sreg_64 }
+ - { id: 3, class: sreg_64_xexec }
- { id: 4, class: vgpr_32 }
- - { id: 5, class: sreg_64 }
+ - { id: 5, class: sreg_64_xexec }
- { id: 6, class: vgpr_32 }
- { id: 7, class: vgpr_32 }
@@ -181,7 +181,7 @@ registers:
- { id: 1, class: vgpr_32 }
- { id: 2, class: vgpr_32 }
- { id: 3, class: vgpr_32 }
- - { id: 4, class: sreg_64 }
+ - { id: 4, class: sreg_64_xexec }
- { id: 5, class: vgpr_32 }
- { id: 6, class: vgpr_32 }
- { id: 7, class: vgpr_32 }
@@ -210,7 +210,7 @@ registers:
- { id: 1, class: vgpr_32 }
- { id: 2, class: vgpr_32 }
- { id: 3, class: vgpr_32 }
- - { id: 4, class: sreg_64 }
+ - { id: 4, class: sreg_64_xexec }
- { id: 5, class: vgpr_32 }
- { id: 6, class: vgpr_32 }
- { id: 7, class: vgpr_32 }
diff --git a/llvm/test/CodeGen/AMDGPU/shrink-carry.mir b/llvm/test/CodeGen/AMDGPU/shrink-carry.mir
index d5d6223cc06..cf000ffa774 100644
--- a/llvm/test/CodeGen/AMDGPU/shrink-carry.mir
+++ b/llvm/test/CodeGen/AMDGPU/shrink-carry.mir
@@ -10,9 +10,9 @@ registers:
- { id: 0, class: vgpr_32 }
- { id: 1, class: vgpr_32 }
- { id: 2, class: vgpr_32 }
- - { id: 3, class: sreg_64 }
+ - { id: 3, class: sreg_64_xexec }
- { id: 4, class: vgpr_32 }
- - { id: 5, class: sreg_64 }
+ - { id: 5, class: sreg_64_xexec }
body: |
bb.0:
@@ -34,9 +34,9 @@ registers:
- { id: 0, class: vgpr_32 }
- { id: 1, class: vgpr_32 }
- { id: 2, class: vgpr_32 }
- - { id: 3, class: sreg_64 }
+ - { id: 3, class: sreg_64_xexec }
- { id: 4, class: vgpr_32 }
- - { id: 5, class: sreg_64 }
+ - { id: 5, class: sreg_64_xexec }
body: |
bb.0:
@@ -58,9 +58,9 @@ registers:
- { id: 0, class: vgpr_32 }
- { id: 1, class: vgpr_32 }
- { id: 2, class: vgpr_32 }
- - { id: 3, class: sreg_64 }
+ - { id: 3, class: sreg_64_xexec }
- { id: 4, class: vgpr_32 }
- - { id: 5, class: sreg_64 }
+ - { id: 5, class: sreg_64_xexec }
body: |
bb.0:
@@ -82,9 +82,9 @@ registers:
- { id: 0, class: vgpr_32 }
- { id: 1, class: vgpr_32 }
- { id: 2, class: vgpr_32 }
- - { id: 3, class: sreg_64 }
+ - { id: 3, class: sreg_64_xexec }
- { id: 4, class: vgpr_32 }
- - { id: 5, class: sreg_64 }
+ - { id: 5, class: sreg_64_xexec }
body: |
bb.0:
diff --git a/llvm/test/CodeGen/AMDGPU/shrink-vop3-carry-out.mir b/llvm/test/CodeGen/AMDGPU/shrink-vop3-carry-out.mir
index 767118eb8d1..b1fdc5f8045 100644
--- a/llvm/test/CodeGen/AMDGPU/shrink-vop3-carry-out.mir
+++ b/llvm/test/CodeGen/AMDGPU/shrink-vop3-carry-out.mir
@@ -27,7 +27,7 @@ registers:
- { id: 6, class: sreg_32 }
- { id: 7, class: sreg_32 }
- { id: 8, class: sreg_32_xm0 }
- - { id: 9, class: sreg_64 }
+ - { id: 9, class: sreg_64_xexec }
- { id: 10, class: sreg_32_xm0 }
- { id: 11, class: sreg_32_xm0 }
- { id: 12, class: sgpr_64 }
@@ -111,7 +111,7 @@ registers:
- { id: 6, class: sreg_32 }
- { id: 7, class: sreg_32 }
- { id: 8, class: sreg_32_xm0 }
- - { id: 9, class: sreg_64 }
+ - { id: 9, class: sreg_64_xexec }
- { id: 10, class: sreg_32_xm0 }
- { id: 11, class: sreg_32_xm0 }
- { id: 12, class: sgpr_64 }
@@ -195,7 +195,7 @@ registers:
- { id: 6, class: sreg_32 }
- { id: 7, class: sreg_32 }
- { id: 8, class: sreg_32_xm0 }
- - { id: 9, class: sreg_64 }
+ - { id: 9, class: sreg_64_xexec }
- { id: 10, class: sreg_32_xm0 }
- { id: 11, class: sreg_32_xm0 }
- { id: 12, class: sgpr_64 }
@@ -278,7 +278,7 @@ registers:
- { id: 6, class: sreg_32 }
- { id: 7, class: sreg_32 }
- { id: 8, class: sreg_32_xm0 }
- - { id: 9, class: sreg_64 }
+ - { id: 9, class: sreg_64_xexec }
- { id: 10, class: sreg_32_xm0 }
- { id: 11, class: sreg_32_xm0 }
- { id: 12, class: sgpr_64 }
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